Presentation
Digitally Assisted Analog Techniques for Next‑Generation Data Converters, Test, and Clocking
DescriptionOver the past two decades, digital logic density has increased by more than three orders of magnitude, while analog metrics such as gain, linearity, and noise have improved only incrementally. Digital calibration and compensation can cut analog design margins by up to 50%, enabling smaller and more power-efficient circuits, while techniques such as dynamic voltage and frequency scaling, algorithmic noise shaping, and digital redundancy consistently deliver order‑of‑magnitude energy savings over analog-only solutions. Furthermore, digital subsystems inherently support in‑situ testability, with scan-based and BIST methods achieving production fault coverage exceeding 99%. Reflecting this shift, modern SoCs are now more than 80% digital—even in RF, clocking, and sensor interfaces. This talk explores how digitally assisted analog techniques are reshaping mixed‑signal design, enabling scalable, low-power, and highly testable solutions for next‑generation systems.
Event Type
Engineering Special Session
TimeTuesday, July 281:30pm - 2:00pm PDT
LocationSeaside Ballroom B