Presentation
ARCHITECT LABS: Ada: A Self-Improving AI System for HW-SW co-Design and Verification
DescriptionAI-agentic flows for chip design have emerged with the potential to create a paradigm shift in the EDA industry. At Architect Labs, we are building the first generation of AI-native design methodology for chip development. In this presentation, we share details on our AI-based automation flow for fast and verifiable generation of frontend design-collaterals, including architectural exploration, software-modeling, RTL, and verification. Our methodology enables capturing the design intent of the architecture based on design specifications, while the human-in-the-loop iterates on the specs as the “architect”. At the core of this methodology, an agentic harness combined with ML methods including reinforcement learning and test-time-scaling achieves fully end-to-end autonomous HW design and verification capability, all while using SOTA EDA tools and proven chip design methods. As a demonstration vehicle, we further present how
our AI system autonomously designed a specialized AI hardware accelerator targeting FPGA deployment for running inference on a SOTA LLM model. In this end-to-end demo, we share details on how our harness performs architectural exploration under memory vs. compute bound workloads to generate performance models, firmware, RTL, AI kernels, and more. We will bring the FPGA for an in-person demo, and share quantitative results on both the methodology and the design results, such as number of engineers, time-to-design, and achieved performance numbers.
our AI system autonomously designed a specialized AI hardware accelerator targeting FPGA deployment for running inference on a SOTA LLM model. In this end-to-end demo, we share details on how our harness performs architectural exploration under memory vs. compute bound workloads to generate performance models, firmware, RTL, AI kernels, and more. We will bring the FPGA for an in-person demo, and share quantitative results on both the methodology and the design results, such as number of engineers, time-to-design, and achieved performance numbers.
Presenter
Event Type
Exhibitor Forum
TimeTuesday, July 283:15pm - 3:45pm PDT
LocationExhibitor Forum, Exhibit Floor