Presentation
GOOGLE: From Infrastructure to AI: Taping Out Data Center Silicon on a Workload-Optimized, Agent-Driven EDA Stack
DescriptionAs semiconductor designs advance toward trillion-transistor systems, general-purpose infrastructure can become a bottleneck, slowing down design velocity and impacting your bottom line. In this session, we'll provide a technical deep dive into the workload-optimized EDA stack that Google uses to tape out its own data center chips —including the Ironwood TPU and ARM-based Axion processors—all entirely on Google Cloud.
We'll explore how to deploy high-performance compute and storage foundations to meet the intense demands of modern chip design. We'll detail how our H4D and C4A instances, paired with Google Cloud NetApp Volumes (GCNV), are engineered to handle the rigorous I/O and low-latency requirements of large-scale verification and physical design. Furthermore, we'll demonstrate how Alphabet is integrating AI directly into the production flow including using agents to optimize Verilog code and achieve targeted improvements in Power, Performance, and Area (PPA), effectively de-risking complex design cycles through a cloud-native, AI-integrated approach.
We'll explore how to deploy high-performance compute and storage foundations to meet the intense demands of modern chip design. We'll detail how our H4D and C4A instances, paired with Google Cloud NetApp Volumes (GCNV), are engineered to handle the rigorous I/O and low-latency requirements of large-scale verification and physical design. Furthermore, we'll demonstrate how Alphabet is integrating AI directly into the production flow including using agents to optimize Verilog code and achieve targeted improvements in Power, Performance, and Area (PPA), effectively de-risking complex design cycles through a cloud-native, AI-integrated approach.
Presenter
Event Type
Exhibitor Forum
TimeWednesday, July 2910:30am - 11:00am PDT
LocationExhibitor Forum, Exhibit Floor