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Normal Computing
Presentations
Work in Progress
Agentic AI for Chip Design and Verification: Results and Limitations from CVDP
5:13pm - 5:14pm PDT Monday, July 27 Exhibit Hall
Exhibitor Forum
Auto-Formalization to Bridge Design Specifications Into Verifiable Hardware Logic
4:00pm - 5:00pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor
AI
EDA
Systems
Exhibitor Forum
NORMAL COMPUTING: AI-Native EDA: Why the Ceiling Is Architectural, Not Model-Dependent
3:15pm - 3:45pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor
Sessions
Research Manuscript
Generative AI and Graph-Based Learning for Next-Gen Circuit & Device Simulation
1:30pm - 3:00pm PDT Monday, July 27 Mtg Room 202AB
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Contributors
Jan Ole Ernst
Johann George
Dmitri Saberi
Rajath Salegame
Session Chairs
Doyun Kim