Organization
Zhejiang University
Presentations
Research Manuscript
Security
SEC2. Hardware Security: Primitives, Architecture, Design & Test
Research Manuscript
AI
AI5-II. AI/ML System and Platform Design
Research Manuscript
EDA
EDA4. Power Analysis and Optimization
Research Manuscript
EDA
EDA9. Test, Validation and Silicon Lifecycle Management
Research Manuscript
EDA
EDA8. Design for Manufacturability and Reliability
Research Manuscript
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Research Manuscript
Security
SEC4. Embedded and Cross-Layer Security
Research Manuscript
Design
DES3. Emerging Models of Computation
Research Manuscript
Systems
SYS6. Time-Critical and Fault-Tolerant System Design
Research Manuscript
Design
DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
EDA
EDA9. Test, Validation and Silicon Lifecycle Management
Research Manuscript
AI
AI5-I. AI/ML System and Platform Design
Research Manuscript
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Security
SEC1. AI/ML Security/Privacy
Research Manuscript
Design
DES2A. In-memory and Near-memory Computing Circuits
Research Manuscript
Design
DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Systems
SYS1. Autonomous Systems (Automotive, Robotics, Drones)
Research Manuscript
Security
SEC3-I. Hardware Security: Attack and Defense
Research Manuscript
Design
Quantum
DES6. Quantum Computing
Research Manuscript
AI
AI3-I. AI/ML Application and Infrastructure
Research Manuscript
Design
Quantum
DES6. Quantum Computing
Research Manuscript
AI
AI5-II. AI/ML System and Platform Design
Sessions
Research Manuscript
Security
SEC4. Embedded and Cross-Layer Security
Research Manuscript
AI2-I. AI/ML Algorithms and Models
Design
DES4. Digital and Analog Circuits; Design
DES1-I. SoC
Heterogeneous
and Reconfigurable Architectures; EDA
EDA4. Power Analysis and Optimization; EDA
EDA2. Design Verification and Validation; Security
SEC4. Embedded and Cross-Layer Security; AI
AI1. AI/ML Frontiers for Hardware Design; AI
Contributors
Session Chairs
