Close

Organization

<
Southeast University
Presentations
Research Manuscript
A Hamiltonian-Guided Pre-Trainer for Variational Quantum Algorithms
2:34pm - 2:47pm PDT Wednesday, July 29 Mtg Room 201B
Design
Quantum
DES6. Quantum Computing
Research Manuscript
A Levelized Load-Balanced and Structure-Adaptive GPU LU Factorization Method for Circuit Simulation
2:34pm - 2:47pm PDT Monday, July 27 Mtg Room 202AB
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Research Manuscript
Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
1:42pm - 1:55pm PDT Wednesday, July 29 Mtg Room 203AB
Design
DES2B-II. In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
Active Imitation Learning for Thermal- and Kernel-Aware LFM Inference on 3D S-NUCA Many-Cores
2:34pm - 2:47pm PDT Tuesday, July 28 Mtg Room 101A
AI
AI3-II. AI/ML Application and Infrastructure
Research Manuscript
Akirarust: Re-Thinking LLM-Aided Rust Repair Using a Feedback-Guided Thinking Switch
12:15pm - 12:30pm PDT Wednesday, July 29 Mtg Room 202C
Systems
SYS3. Embedded Software
Research Manuscript
Algorithm and Hardware Co-Design for Efficient Complex-Valued Uncertainty Estimation
1:30pm - 1:42pm PDT Tuesday, July 28 Mtg Room 202C
Design
DES3. Emerging Models of Computation
Research Manuscript
Are They All Safe? Practical Fault Injection Attacks on FPGA Logic Synthesis Tools
4:30pm - 4:42pm PDT Wednesday, July 29 Mtg Room 202C
Security
SEC2. Hardware Security: Primitives, Architecture, Design & Test
Research Manuscript
Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells
3:30pm - 3:42pm PDT Tuesday, July 28 Mtg Room 203AB
EDA
EDA7-II. Physical Design and Verification
Research Manuscript
Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
3:42pm - 3:54pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA2. Design Verification and Validation
Research Manuscript
Cell-Structure-Independent Transistor-Level Placement and MOL-Aware Routing Framework Beyond the Standard-Cell Paradigm
3:42pm - 3:54pm PDT Wednesday, July 29 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
3:30pm - 3:42pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
5:18pm - 5:30pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Circuitdiff: Bridging Netlist Knowledge with RTL Based on Graph Denoising Diffusion
11:36am - 11:50am PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Cupilot: A Strategy-Coordinated Multi-Agent Framework for CUDA Kernel Evolution
1:42pm - 1:55pm PDT Monday, July 27 Mtg Room 101A
AI
AI2-I. AI/ML Algorithms and Models
Research Manuscript
DCTS: Differentiable Clock Tree Synthesis Based on Probabilistic Graphical Model
4:18pm - 4:30pm PDT Tuesday, July 28 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
DIA-CIM: A Dynamic Iterative Aggregation Graph Neural Network and Its Hardware Co-Design for Energy-Efficient Graph Processing
11:10am - 11:23am PDT Monday, July 27 Mtg Room 203AB
Design
DES2A. In-memory and Near-memory Computing Circuits
Research Manuscript
DiffDEG: Diffusion-Enhanced Design Evolution Graph Representation Learning for Post-Layout Optimization
1:42pm - 1:55pm PDT Tuesday, July 28 Mtg Room 101A
AI
AI3-II. AI/ML Application and Infrastructure
Research Manuscript
Expcheck: Dynamic Expert-Aware Checkpointing for Mixture-of-Experts Based Models
4:30pm - 4:42pm PDT Wednesday, July 29 Mtg Room 203C
Systems
SYS5. Embedded Memory and Storage Systems
Research Manuscript
From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
10:43am - 10:56am PDT Tuesday, July 28 Mtg Room 202C
Systems
SYS2. Design of Cyber-Physical Systems and IoT
Research Manuscript
Gearls: Generalizable Reinforcement Learning Framework for Logic Optimization via Policy Similarity Metric
3:43pm - 3:56pm PDT Tuesday, July 28 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Research Manuscript
HYPER-CIM: Hierarchical Predictive Exploration and Realizable Design Flow for High-Efficient Digital CIM
10:43am - 10:56am PDT Monday, July 27 Mtg Room 203AB
Design
DES2A. In-memory and Near-memory Computing Circuits
Research Manuscript
Insights from Verification: Training a Verilog Generation LLM Using Reinforcement Learning with Testbench Feedback
11:10am - 11:23am PDT Monday, July 27 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Late Breaking Results
Late Breaking Results: A Coarse-to-Fine PCB Placement Framework via LLM-Guided Component Grouping and Group-Aware Placement
5:29pm - 5:32pm PDT Monday, July 27 Exhibit Hall
Late Breaking Results
Late Breaking Results: A Fully Differentiable Rectilinear Minimum Spanning Tree Wirelength Model for Global Placement
6:30pm - 6:34pm PDT Monday, July 27 Exhibit Hall
Late Breaking Results
Late Breaking Results: LLM-Driven Constraint Generation and Deferred Shape Exploration for Analog IC Floorplanning
6:43pm - 6:47pm PDT Monday, July 27 Exhibit Hall
Late Breaking Results
Late Breaking Results: Merge-Aware Placement and DP-Based Wave Propagation Routing for Scalable Flip-FET Cell Layout Synthesis
6:37pm - 6:40pm PDT Monday, July 27 Exhibit Hall
Late Breaking Results
Late Breaking Results: Physics-Aware Diffusion Framework for Transistor-Level Placement Beyond Standard-Cell Boundary
5:00pm - 5:03pm PDT Monday, July 27 Exhibit Hall
Research Manuscript
Legotherm: Modular and Reusable Thermal Model for Chiplet-Based Heterogeneous Integration
5:06pm - 5:18pm PDT Monday, July 27 Mtg Room 202AB
EDA
EDA4. Power Analysis and Optimization
Research Manuscript
LLMVA: LLMs Empowered Verilog-A Iterative for MRAM Design Technology Co-Optimization
1:42pm - 1:55pm PDT Tuesday, July 28 Mtg Room 101B
EDA
EDA8. Design for Manufacturability and Reliability
Research Manuscript
Maple: Efficient Data-Transfer-Aware Mapping Exploration for NDP-Enabled Edge LLM Inference
11:36am - 11:50am PDT Tuesday, July 28 Mtg Room 203AB
Design
DES2B-I. In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
11:18am - 11:30am PDT Wednesday, July 29 Mtg Room 202AB
EDA
EDA2. Design Verification and Validation
Research Manuscript
NVLLM: A 3D NAND-Centric Architecture Enabling Edge on-Device LLM Inference
12:03pm - 12:16pm PDT Tuesday, July 28 Mtg Room 203AB
Design
DES2B-I. In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
Optimized Time-Dependent Hamiltonian Evolution Quantum Solver for Power System Transient Computations
2:47pm - 3:00pm PDT Wednesday, July 29 Mtg Room 201B
Design
Quantum
DES6. Quantum Computing
Research Manuscript
Paretopilot: Global Optimization Reasoning on HLS Design Space Exploration with LLMs
1:55pm - 2:08pm PDT Monday, July 27 Mtg Room 101A
AI
AI2-I. AI/ML Algorithms and Models
Research Manuscript
Path-Based Timing Analysis Acceleration via Segment-Level Timing Arc Reuse
10:30am - 10:43am PDT Monday, July 27 Mtg Room 202AB
EDA
EDA3. Timing Analysis and Optimization
Research Manuscript
Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging
1:55pm - 2:08pm PDT Monday, July 27 Mtg Room 203C
Systems
SYS4. Embedded System Design Tools and Methodologies
Research Manuscript
Rectilinear Soft Module Floorplanning via Differentiable Polygon Shaping Model and Flow-Based Legalization
4:06pm - 4:18pm PDT Tuesday, July 28 Mtg Room 203AB
EDA
EDA7-II. Physical Design and Verification
Research Manuscript
SALUT: Efficient Sparse LU Factorization via Asynchronous Task Triggering on HBM FPGAs
4:30pm - 4:42pm PDT Tuesday, July 28 Mtg Room 202C
Design
DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Strix: Re-Thinking NPU Reliability from a System Perspective
10:30am - 10:43am PDT Wednesday, July 29 Mtg Room 203C
Systems
SYS6. Time-Critical and Fault-Tolerant System Design
Research Manuscript
Toward True-3D Timing-Driven Analytical Global Placement for Mixed-Size Face-to-Face 3D ICs
4:18pm - 4:30pm PDT Wednesday, July 29 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
Uvmarvel: an Automated LLM-Aided UVM Machine for Subsystem-Level RTL Verification
4:06pm - 4:18pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA2. Design Verification and Validation
Research Manuscript
ZK-Tracer: A High-Performance Heterogeneous Accelerator for Zero-Knowledge VM Trace Generation
3:54pm - 4:06pm PDT Wednesday, July 29 Mtg Room 203AB
Design
DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures
Contributors
Hao Cai
Peng Cao
Jinwu Chen
Lixin Chen
Pengju Chen
Qiyuan Chen
Yu Chen
Haoyu Cui
Jieran Cui
Yizhi Ding
Haoran Du
Yushu Du
Chenchen Fu
Lixin Ge
Hao Gu
An Guo
Xiaomeng Han
Ziyue Han
Mingbo Hao
Xiangfei Hu
Yuchen Hu
Fuxing Huang
Junming Jiao
Tianhui Jiao
He Li
Junhong Li
Min Li
Runkai Li
Xiaodong Li
Zhi Li
Bo Liu
Jiyuan Liu
Tianyang Liu
Xiang Liu
xinning liu
Jiaqi Lyu
Yanlong Mao
Xiangyi Meng
Cheng Ni
Dan Niu
Keyu Peng
Zhangrui Qian
Yusen Qin
qingsheng qiu
Lizheng Ren
Weiwei Shan
Weiwei Shan
Chaoyao Shen
Chenpu Shi
Longxing Shi
Yuhui Shi
Xin Si
Jiongzhe Su
Shengchu Su
Jialin Sun
Mengdi Sun
Yongming Tang
Leyun Tian
Qi Tian
Qixun Tian
Baoping Wang
Chao Wang
Huanghui Wang
Hui Wang
Tinglue Wang
Xi Wang
zhaohan wang
Zhengkai Wen
Defa Wu
Defa Wu
Hao Wu
Liangji Wu
Weiwei Wu
Yinuo Wu
Renjie Xia
Jia Xiong
Guorui Xu
Jiajie Xu
Ke Xu
Zhihao Xu
Changwei Yan
Hao Yan
Yan Yan
Zhihao Yan
Jun Yang
Jun Yang
Jun Yang
Jianmin Ye
Junhao Ye
Dean You
han zhang
Jie Zhang
Mingchi Zhang
Yifan Zhang
Yuhuai Zhang
Zhaoyang Zhang
Taotao Zhao
Zhengzhe Zheng
Xiaoxue Zhong
Jie Zhou
yingxuan zhou
Quanhai Zhu
Yinan Zhu
Ziran Zhu
Yunfan Zuo