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Cadence Design Systems, Inc.
Presentations
Engineering Presentation
A Rule-Aware Layout Conversion Framework for Back-End Physical Design
1:45pm - 2:00pm PDT Wednesday, July 29 Seaside RM 7
EDA
Engineering Poster
A Scalable Timing Analysis and Closure Methodology for Ultra-Large Designs
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Accelerating CPU Design in Advanced Nodes with AI-Powered Floor Planning and VT Optimization
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Activity Reloaded: Joules Flash Replay - A Methodology for Accurate, Delay-Based Activity Generation for Driving Optimization and Power Sign-off
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Advancing CDC Formal Verification in Low-Power SoCs Using Power Intent and Smart Waiver Techniques
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Agentic AI Partition And Floorplan Assistance For PCIe/CXL Subsystem Physical Design
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
11:45am - 12:00pm PDT Monday, July 27 Seaside RM 7
Chiplet
EDA
Engineering Presentation
Auto-Chk: Closing the Last-Mile Interpretation Gap in Digital Sign-off via a Neuro-Symbolic Compiler Framework
10:30am - 10:45am PDT Tuesday, July 28 Seaside RM 7
EDA
Security
Engineering Presentation
Automated Validation of Liberty Models
2:45pm - 3:00pm PDT Monday, July 27 Seaside Ballroom B
AI
Design
EDA
Engineering Presentation
Automated Verification and Performance Analysis for Chiplets
10:48am - 11:06am PDT Monday, July 27 Seaside Ballroom B
AI
EDA
Systems
Engineering Poster
Breaking Sequential Depth Barriers: An FSM-Driven Bridge for the Formal Verification of Virtually Address-Mapped Hardware Registers
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster Gladiator
BSPDN: A Power Delivery Architecture for 19.8% Core Power Reduction and 9.3C Thermal Mitigation in Next-Generation AI Processors
5:00pm - 5:08pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Exhibitor Forum
CADENCE DESIGN SYSTEMS: LLMs in Production With Chip Teams: Opportunities, Challenges, and Lessons Learned
10:30am - 11:00am PDT Monday, July 27 Exhibitor Forum, Exhibit Floor
Engineering Poster
Cognitively Guided EM-Aware Routing Approach for Efficient Layout Implementation
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
CPPR-Aware Tap-Point Reassignment in Flex-H and Multi-Point CTS for Timing Closure in High-Performance Cores
2:30pm - 2:45pm PDT Wednesday, July 29 Seaside RM 7
EDA
Engineering Presentation
Crosstalk Effect Prediction and Optimization for Detail Routing Using CNN Models and Reinforcement Learning Flow Framework
2:15pm - 2:30pm PDT Wednesday, July 29 Seaside RM 7
EDA
Engineering Poster
Crosstalk Hotspot Map Creation at Placement Stage Using CNN UNET Prediction Model
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Custom Implementation of High-Speed Digital Blocks Using Virtuoso Studio
11:45am - 12:00pm PDT Tuesday, July 28 Seaside Ballroom B
Design
EDA
Systems
Engineering Poster
Design Rule Checking for Rigid-Flex PCB
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
ECO Strategy for BIG DIE SOC Convergence
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Efficient IR-Aware Powergrid Optimization
4:15pm - 4:30pm PDT Monday, July 27 Seaside Ballroom A
EDA
Systems
Engineering Poster
From Broken Regression to Root-Cause Commit in One Click A Two-Stage Regression-Aware Git-Bisect Framework for Large-Scale Hardware Verification
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
From Concept to PPA Confidence - Methodology for Rapid RTL Evaluation and Signoff with Joules RTL Design Studio.
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Fully Automated On‑Chip Inductor Synthesis for High‑Frequency VCO with ML Based Optimization Flow
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Special Session
Gaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect?
1:30pm - 3:00pm PDT Tuesday, July 28 Seaside Ballroom A
AI
EDA
Systems
Engineering Poster
Implementing Secure Boot, Attestation and Secure Storage in Systems in Package
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Research Panel
Is the EDA Industry Fundamentally Ill-Prepared for True 3D Heterogeneous Integration?
10:30am - 12:30pm PDT Tuesday, July 28 Mtg Room 104A
EDA
Engineering Poster
Matching Constraint Driven Synchronous Array Implementation for High-Performance ADCs
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Mixed Transistor Design Closure
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Multi-Cycle Dynamic Vectorless Analysis for Improved PDN Signoff
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Research Panel
New Minds, New Models: Who Will Drive AI-Led Design Innovation?
10:30am - 12:30pm PDT Monday, July 27 Mtg Room 104A
AI
Engineering Poster
Next-Generation 3DIC STCO: AI-Enabled PPA and Cost Optimization Through IEEE P3537 3Dblox
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Solving Memory Subsystem Verification Challenges for Multi-Instance Designs
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Structure Aware Clock Tree Synthesis Using Width-Driven CTS Cell Constraints
2:45pm - 3:00pm PDT Wednesday, July 29 Seaside RM 7
EDA
Engineering Poster
User Definable Custom Primitives in 3DIC AI-Driven STCO: Case Study on Power Grid Optimization for IR Enhancement
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Using Arm Native Acceleration with VLAB Virtual Platforms
4:30pm - 4:45pm PDT Monday, July 27 Seaside Ballroom B
Design
EDA
Systems
Research Panel
Who Verifies the Verifier? Trust and Accountability in the Age of Autonomous EDA Agents
1:30pm - 3:00pm PDT Monday, July 27 Mtg Room 104A
AI
Sessions
Research Manuscript
RM Poster Session One
12:30pm - 1:00pm PDT Monday, July 27 Mtg Room 102
AI
DES5. Emerging Device and Interconnect Technologies
AI4-I. AI/ML Architecture Design; EDA
EDA5. RTL/Logic Level and High-level Synthesis; Security
SEC1. AI/ML Security/Privacy; AI
AI1. AI/ML Frontiers for Hardware Design; Design
DES2A. In-memory and Near-memory Computing Circuits; EDA
EDA3. Timing Analysis and Optimization; Design
Research Manuscript
Silicon Whisperers: When LLMs Learn to Speak RTL
3:30pm - 5:30pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Engineering Presentation
Strong Foundations Lead to High Impact Gains
1:30pm - 3:00pm PDT Tuesday, July 28 Seaside RM 7
Design
EDA
Research Manuscript
From Analog to 3D Packaging: Enabling Routing and Clocking for Next-Generation Systems
3:30pm - 5:30pm PDT Tuesday, July 28 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
RM Poster Session Six
5:30pm - 6:00pm PDT Tuesday, July 28
EDA7-II. Physical Design and Verification
Design
EDA5. RTL/Logic Level and High-level Synthesis; Security
DES1-I. SoC
Heterogeneous
and Reconfigurable Architectures; AI
AI2-II. AI/ML Algorithms and Models; EDA
EDA7-I. Physical Design and Verification; AI
AI5-I. AI/ML System and Platform Design; EDA
SEC2. Hardware Security: Primitives
Architecture
Design & Test; EDA
Contributors
Nimish Agashiwala
Charles Alpert
Chetan B S
Daksh Bakshi
Akshita Bansal
Batu Bayram
Sonia Beghum
Sachin Bhasin
Sai Sri Ram Goud Chamakuri
Manish Chand
Pinhong Chen
Wentao Dai
Gaurav Dhawan
Amit Dhuria
Harish G
yuwenyuan gao
Tarakeshwar Goud D
Matt Graham
Weifeng Gu
Mohit Gupta
Ruchin Gupta
Ziyad Hanna
Kartik Hegde
Prayes Jain
Nikhil Jatana
WoongSik Jung
Lakshmidas K
Juhyun Kang
Ayush Khare
Pratik Korde
Ravinder Kumar
Vishesh Kumar
Joshua Lam
Chen Li
Jun Lu
Raghu M S
Omang Mahure
K Manimaran
Keshava Manimunda
Merin Meyn
Greg Milano
Harivenkadesh Mohanraj
Loknath Moogi
Chaya N
Arvind NV
Atanas Parashkevov
Vinay Patwardhan
Harshit Pratik
Sumanth S
Erik Seligman
Erik Seligman
Gowry Shanmugam
Shyam Sharma
Rohit Somwanshi
Mahesh Subramanian
Himanshu Tanwar
Junie Um
Alok Verma
Jeremy Wazny
Tom Weiss
Xukang Wu
Xiaohu Xu
Hanqi Yang
Gwanghoon Yun
Ran Zhao
Session Chairs
Nimish Agashiwala
Amin Farshidi
Radharamanan Radhakrishnan
Hamid Shojaei