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Fudan University
Presentations
Research Manuscript
A Boolean Processor-Based Hardware Emulation System with Reconfigurable Interconnects
4:42pm - 4:54pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA2. Design Verification and Validation
Research Manuscript
AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning
5:18pm - 5:30pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA2. Design Verification and Validation
Research Manuscript
Amoeba: Runtime Tensor Parallel Transformation for LLM Inference Services
4:06pm - 4:18pm PDT Tuesday, July 28 Mtg Room 101B
AI
AI5-I. AI/ML System and Platform Design
Research Manuscript
Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells
3:30pm - 3:42pm PDT Tuesday, July 28 Mtg Room 203AB
EDA
EDA7-II. Physical Design and Verification
Research Manuscript
ASG-MOENN: Adaptive Sparsely-Gated Mixture of Experts Neural Network for Digital Predistortion in Quadrature Switched-Capacitor Power Amplifiers
2:08pm - 2:21pm PDT Tuesday, July 28 Mtg Room 101A
AI
AI3-II. AI/ML Application and Infrastructure
Research Manuscript
Dataflowgen: An MLIR-Based Compiler for Efficient Dataflow Accelerator Generation
2:34pm - 2:47pm PDT Monday, July 27 Mtg Room 201B
Chiplet
EDA
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package
Research Manuscript
Drcagent: A Design Rule Aware LLM Agent for DRC Auto-Fix with Adversarial Reinforcement Learning
5:06pm - 5:18pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
DRCGen: A Controllable DRC Violation Case Generator with Cross-PDK Transferability for Rule-Deck and Tool Validation
4:42pm - 4:54pm PDT Tuesday, July 28 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
Duet: Exploiting High-Order Lossless Sparsity for Bit-Serial Transformer Acceleration via Distribution-Aware Pruning
10:56am - 11:10am PDT Wednesday, July 29 Mtg Room 101B
AI
AI5-I. AI/ML System and Platform Design
Research Manuscript
Dynamic-Cost Area Recovery for Fracturable LUT-Based FPGAs
4:50pm - 5:03pm PDT Tuesday, July 28 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Engineering Poster
Enhancing Thermal Aware Optimization for 3D Heterogeneous Chiplets Integration: A System-Technology Co-Optimization (STCO) Perspective on Spatial-Temporal Temperature Uniformity
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Research Manuscript
Floquet-Based Subspace Projection Method for Time-Domain PPV Computation
2:21pm - 2:34pm PDT Monday, July 27 Mtg Room 202AB
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Research Manuscript
HierPAS: Accelerating Video Generation Models with Hierarchical Precision and Adaptive Sparsity
1:55pm - 2:08pm PDT Wednesday, July 29 Mtg Room 101B
AI
AI3-II. AI/ML Application and Infrastructure
Research Manuscript
Is 2D Gaussian Enough? A Sort-Free 3D Gaussian Splatting Inference Architecture with Geometry Guidance
12:16pm - 12:30pm PDT Wednesday, July 29 Mtg Room 101A
AI
AI4-I. AI/ML Architecture Design
Late Breaking Results
Late Breaking Results: 3D Analytical Placement with Smoothed Multi-Die Wirelength Model
6:47pm - 6:50pm PDT Monday, July 27 Exhibit Hall
Late Breaking Results
Late Breaking Results: Scalable OARSMT Generation via Predictive Topological Reduction in VLSI Routing
6:04pm - 6:08pm PDT Monday, July 27 Exhibit Hall
Research Manuscript
Learning the "why": Causal-Aware Learning in Explainable and Efficient CPU Design Optimization
10:56am - 11:10am PDT Tuesday, July 28 Mtg Room 101B
AI
AI5-II. AI/ML System and Platform Design
Research Manuscript
LiveVLM: Efficient Online Video Understanding via Streaming-Oriented KV Cache and Retrieval
4:18pm - 4:30pm PDT Monday, July 27 Mtg Room 101B
AI
AI2-I. AI/ML Algorithms and Models
Research Manuscript
Pcbgen: Self-Evolving LLM Agent for Specification-to-Schematic PCB Design with Parameter Tuning
4:06pm - 4:18pm PDT Wednesday, July 29 Mtg Room 101B
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Research Manuscript
Pefoo-L: A General Framework for Preconditioned Forward-Only Optimizer Enabling LLM Fine-Tuning on the Edge
4:06pm - 4:18pm PDT Tuesday, July 28 Mtg Room 101A
AI
AI2-II. AI/ML Algorithms and Models
Research Manuscript
PEL: A 4K@120FPS Palette-Based Enhancement Layer Validated with JPEG XS Achieving 18.13% Bdrate Reduction
5:18pm - 5:30pm PDT Monday, July 27 Mtg Room 203AB
Design
DES4. Digital and Analog Circuits
Research Manuscript
Perifi:physics-Infused RF Inverse Design with Parametric Data-Efficient Feasible-Region Sampling
3:54pm - 4:06pm PDT Wednesday, July 29 Mtg Room 101B
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Research Manuscript
Towards Fast and Robust Split Federated Learning over Satellite-Based Computing Networks
12:16pm - 12:30pm PDT Wednesday, July 29 Mtg Room 101B
AI
AI5-I. AI/ML System and Platform Design
Contributors
Zhaori Bi
Xianfeng Cao
Shunjie Chang
Guohao Chen
Haoyu Chen
Haoyu Chen
Jianli Chen
Jianli Chen
Zhe Chen
Hanyang Cui
Wenchao Ding
Yuxuan Dong
Yibo Fan
Tianning Gao
Yue Gao
Chenlong He
You Hu
Zhangqi Huang
Qihao Jin
Minge Jing
Long Kong
Jinmei Lai
Jiangnan Li
Muhan Li
Wei Li
Yicheng Li
Yu Li
Heng Liao
Yinyin Lin
Changxu Liu
Haodong Lu
Zihang Ma
Hongyang Pan
Ruiyao Pu
Zhinan Qin
Li Shang
Kejia Shi
Yifan Song
Yangfeng Su
Faxian Sun
Chenyi Tan
Xingyu Tong
Zhuoheng Wan
Jiahao Wang
Kun Wang
Lingli Wang
Siwen Wang
Xin Wang
Yuanfang Wang
Zhiang Wang
Yiming Wei
Liangji Wu
Youran Wu
Hetao Xu
Hongtao Xu
Yuncheng Xu
Changhao Yan
Fan Yang
Jiayu Yang
Shijie Yao
Yun Yin
Jun Yu
Xuan Zeng
Runzhou Zhang
Yehao Zhang
Yifan Zhang
Yuxin Zhang
Zexu Zhang
Zhengyi Zhang
Jin Zhao
Wending Zhao
Yiyang Zhao
Kaixiang Zhu
Keren Zhu
Wenjun Zhu