Organization
The Chinese University of Hong Kong
Presentations
Research Manuscript
Design
DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Research Manuscript
AI
AI5-I. AI/ML System and Platform Design
Research Manuscript
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Research Manuscript
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
EDA
EDA4. Power Analysis and Optimization
Research Manuscript
Chiplet
EDA
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package
Research Manuscript
Chiplet
EDA
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package
Research Manuscript
Systems
SYS6. Time-Critical and Fault-Tolerant System Design
Research Manuscript
Design
Quantum
DES6. Quantum Computing
Research Manuscript
EDA
EDA8. Design for Manufacturability and Reliability
Research Manuscript
EDA
EDA8. Design for Manufacturability and Reliability
Research Manuscript
EDA
EDA3. Timing Analysis and Optimization
Research Manuscript
AI
AI3-II. AI/ML Application and Infrastructure
Research Manuscript
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Research Manuscript
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
EDA
EDA8. Design for Manufacturability and Reliability
Research Manuscript
Systems
SYS5. Embedded Memory and Storage Systems
Research Manuscript
Chiplet
EDA
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package
Research Manuscript
Design
DES2B-II. In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
EDA
EDA8. Design for Manufacturability and Reliability
Research Manuscript
EDA
EDA4. Power Analysis and Optimization
Research Manuscript
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
Design
DES5. Emerging Device and Interconnect Technologies
Late Breaking Results
Work in Progress
Research Manuscript
Design
DES3. Emerging Models of Computation
Research Manuscript
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Research Manuscript
Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
11:18am - 11:30am PDT Wednesday, July 29 Mtg Room 202ABEDA
EDA2. Design Verification and Validation
Research Manuscript
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
EDA
EDA7-II. Physical Design and Verification
Research Manuscript
EDA
EDA3. Timing Analysis and Optimization
Research Manuscript
AI
AI2-I. AI/ML Algorithms and Models
Research Manuscript
Design
DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
AI
AI2-II. AI/ML Algorithms and Models
Research Manuscript
EDA
EDA4. Power Analysis and Optimization
Research Manuscript
Design
DES2B-I. In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
EDA
EDA3. Timing Analysis and Optimization
Late Breaking Results
Research Manuscript
Systems
SYS5. Embedded Memory and Storage Systems
Research Manuscript
Design
DES5. Emerging Device and Interconnect Technologies
Research Manuscript
Security
SEC2. Hardware Security: Primitives, Architecture, Design & Test
Research Manuscript
AI
AI2-II. AI/ML Algorithms and Models
Research Manuscript
AI
AI4-II. AI/ML Architecture Design
Research Manuscript
Systems
SYS5. Embedded Memory and Storage Systems
Sessions
Research Manuscript
Quantum
DES3. Emerging Models of Computation
EDA
EDA8. Design for Manufacturability and Reliability; Design
DES6. Quantum Computing; Chiplet
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package; Systems
SYS5. Embedded Memory and Storage Systems; AI
AI3-II. AI/ML Application and Infrastructure; Design
Contributors
Session Chairs