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NXP
Presentations
Engineering Poster Gladiator
A Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance Nodes
2:11pm - 2:22pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Achieving "zero Defect" Quality in Automotive Ethernet Solutions with AI-Accelerated Trimming & Verification
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Automated Validation of Liberty Models
2:45pm - 3:00pm PDT Monday, July 27 Seaside Ballroom B
AI
Design
EDA
Engineering Poster
Breaking the Simulation Wall – Practical Acceleration for Pre-Silicon Validation
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Central DMA IP Verification Using Layered UVM Scoreboard
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Early, Efficient and Scalable Parasitic-Aware Layout Design Methodology for High-Precision ICs
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Identifying Weakest Links: A Cell Scoring Metric for Robust Design in Advanced Nodes
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Liberty-Based Profiling for IP Benchmarking
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
ML Based Design Space Prediction for Power Grid Optimization
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Multi-Agent Automated Formal Verification for Automative Applications
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Tackling Local Noise Coverage Limitations in Transient EMIR Analysis for Robust SoC-Level PDN Closure
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Contributors
Tauqueer Alam
Ekansh Bhatnagar
MANOJ CHAHANDE
Krishanu Dey
Sundarraj Durairaj
Abhinav Gaur
Pramod Gayakwad
santhosh kamatam
Vaibhav Kumar
Roopa Malakannavar
Emmanuele Mazzará
Akhilesh Mishra
Ganesha Moorthy Krishnasamy
Khushboo Rathore
Jagadish Rongali
Ragavendar Swamisai