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Synopsys
Presentations
Engineering Poster Gladiator
3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration
5:17pm - 5:25pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
A Compact Digital IP for FMCW Chirp Linearity Monitoring in Automotive Radar Systems
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale Serdes Designs
11:15am - 11:30am PDT Tuesday, July 28 Seaside Ballroom B
Design
EDA
Systems
Engineering Presentation
A Hierarchical and Scalable Power Supply Network (PSN) Analysis Framework for FCBGA Packages in High-Power AI Applications
4:00pm - 4:15pm PDT Monday, July 27 Seaside Ballroom A
EDA
Systems
Engineering Presentation
A Probe-Based Time-Domain Methodology for Dynamic Thermal Management in Stacked-Die Architectures
11:30am - 11:45am PDT Monday, July 27 Seaside RM 7
Chiplet
EDA
Engineering Poster Gladiator
A Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance Nodes
2:11pm - 2:22pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper Generation
4:30pm - 4:45pm PDT Tuesday, July 28 Seaside Ballroom A
Design
EDA
Engineering Poster
Accelerating IR and Timing Convergence with Revolutionary IR-ECO
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
AI‑Assisted Formal Verification: Improving Practical Adoption and Scalability
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
AI-Driven Co-Optimization of Power Delivery Network for High-Power Cores in 2.5D Advanced Packaging
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
An Adaptive Dynamic Power Reduction Technique for Digital Filters
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
An Adjustable Length Compression Method for MBIST Repair Information
11:30am - 11:45am PDT Tuesday, July 28 Seaside RM 7
EDA
Security
Engineering Presentation
Analysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous Integration
4:45pm - 5:00pm PDT Monday, July 27 Seaside Ballroom A
EDA
Systems
Engineering Presentation
Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
11:00am - 11:15am PDT Wednesday, July 29 Seaside Ballroom B
Design
EDA
Security
Systems
Engineering Poster
Beyond Hierarchical Static Verification: Smart Stubbing for Next-Gen AI Accelerators
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Research Panel
Bridging Quantum, AI, and EDA: The Next Frontier of Design Automation
10:30am - 12:30pm PDT Wednesday, July 29 Mtg Room 104A
Design
Engineering Special Session
Challenges and Solutions in the next-Generation Emulation and Prototyping Solutions
3:30pm - 4:00pm PDT Tuesday, July 28 Seaside RM 7
AI
Chiplet
EDA
Systems
Engineering Poster
Channel Width Optimization for IR Drop Reduction in Advanced SoCs
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
DAC Pavilion Panel
Cooley's DAC Troublemaker Panel
3:00pm - 3:45pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
Design
EDA
EDA
Design
Engineering Poster
Differential Validator: Ensuring SoC ROM to Hierarchical Blocks Node Voltage Integrity
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Early Thermal Analysis and Silicon Correlation for Face-to-Face 3DIC Physical Design
11:15am - 11:30am PDT Monday, July 27 Seaside RM 7
Chiplet
EDA
Engineering Poster
Early, Efficient and Scalable Parasitic-Aware Layout Design Methodology for High-Precision ICs
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster Gladiator
Efficient Electromagnetic Extraction of Superconducting Circuits Used with Quantum Computers and Rapid Single Flux Quantum Designs
5:34pm - 5:42pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Efficient Power Management in USB4 Routers
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Enabling Early Thermal Insight in Heterogeneous Integration Through Implementation-Driven Power Modeling
4:30pm - 4:45pm PDT Monday, July 27 Seaside Ballroom A
EDA
Systems
Engineering Poster
Enhancing Thermal Aware Optimization for 3D Heterogeneous Chiplets Integration: A System-Technology Co-Optimization (STCO) Perspective on Spatial-Temporal Temperature Uniformity
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Fair Play in the Multiplex: Formal Verification of Complex Arbmux Designs
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Formally Validating Industry Standard BCH‑ECC/CRC Codes – A Step by Step Recipe
3:45pm - 4:00pm PDT Tuesday, July 28 Seaside Ballroom A
Design
EDA
Engineering Presentation
From Design to Defense: Pioneering Pre-Silicon Leakage Detection for Novel ECC Crypto Core
11:15am - 11:30am PDT Wednesday, July 29 Seaside Ballroom B
Design
EDA
Security
Systems
Engineering Special Session
Gaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect?
1:30pm - 3:00pm PDT Tuesday, July 28 Seaside Ballroom A
AI
EDA
Systems
Engineering Poster
Hierarchical Cost-Efficient IR Methodology for AI SoCs
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Research Panel
Is the EDA Industry Fundamentally Ill-Prepared for True 3D Heterogeneous Integration?
10:30am - 12:30pm PDT Tuesday, July 28 Mtg Room 104A
EDA
Late Breaking Results
Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond
6:01pm - 6:04pm PDT Monday, July 27 Exhibit Hall
Engineering Presentation
Leveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.ai
2:00pm - 2:15pm PDT Monday, July 27 Seaside Ballroom B
AI
Design
EDA
Engineering Poster
Low Power Optimization Through Fast and Accurate Time-Based Power Analysis
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
ML Based Design Space Prediction for Power Grid Optimization
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Work in Progress
ML-Net: Enhanced Interconnect Modeling Through Machine Learning–based Framework and Novel Double-π Networks
5:15pm - 5:15pm PDT Monday, July 27 Exhibit Hall
Engineering Presentation
Modeling and Optimization of Power MOSFET Device Layouts with Optislang Tool
2:30pm - 2:45pm PDT Tuesday, July 28 Seaside RM 7
Design
EDA
Engineering Poster Gladiator
Multi Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN Model
5:51pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
No Credit Where Credit Is Due: Quiesced Formal Check for PCIe Crediting
10:45am - 11:00am PDT Tuesday, July 28 Seaside Ballroom B
Design
EDA
Systems
Engineering Poster
Novel Approach to Signoff Large MRAM Memory IP Using Hierarchical Flow
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster Gladiator
Outsmarting State Space Complexity Through Proven Reset Abstraction Stratergies
5:37pm - 5:45pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Overcoming Accuracy and Scalability Limits in Multi-Port On-Chip Electromagnetic Simulation Using a Hybrid Partial Elements Equivalent Circuit Solver
2:45pm - 3:00pm PDT Tuesday, July 28 Seaside RM 7
Design
EDA
Engineering Poster
Physics-Aware CNN-Based IR Drop Risk Prediction for Fast and Reliable SRAM Placement Optimization
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Plug-and-Verify Using Real USB Devices for Front-End Host DUT RTL Validation
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Reduced Order Modelling (ROM) Based Full Chip EMIR Signoff
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Research on Warpage Simulation Fitting, Stress Simulation Method and Glass Substrate Application of Advanced Package for AI Chips
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Special Session
Role of FPGAs in Emulation and Prototyping Systems
4:30pm - 5:00pm PDT Tuesday, July 28 Seaside RM 7
AI
Chiplet
EDA
Systems
Engineering Special Session
Role of HW Based Tools like Emulation and Prototyping in Semiconductor Design Methodology
4:00pm - 4:30pm PDT Tuesday, July 28 Seaside RM 7
AI
Chiplet
EDA
Systems
Research Manuscript
Shared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen Synthesis
4:36pm - 4:50pm PDT Tuesday, July 28 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Engineering Poster Gladiator
Sigma Profiling: Profiling Solution for Power Integrity Signoff
2:22pm - 2:33pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Slack-Exploiting Load Splitting for IR-Drop Mitigation
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Work in Progress
Spec2Plan: A Robust LLM-Powered Framework for Verification Plan Generation and Evaluation
6:40pm - 6:41pm PDT Monday, July 27 Exhibit Hall
Exhibitor Forum
SYNOPSYS: How Silicon Startups Are Addressing the AI Memory Gap
5:15pm - 5:45pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor
Engineering Poster
Tackling Local Noise Coverage Limitations in Transient EMIR Analysis for Robust SoC-Level PDN Closure
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Transforming Linux Drivers for Pre-Silicon Verification and Emulation Using Systemverilog DPI-C
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
UCIe-A 64GT/s High Speed Integrated Design and SI/PI Comparison of CoWoS-S/L/R
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Research Manuscript
Unlocking Automated Datapath Gating via Machine Learning Power Prediction
11:23am - 11:36am PDT Monday, July 27 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Engineering Poster
Vmin Reliability Through Critical Path-Aware PDN Analysis
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Weeding Out Timing Gaps and Improving Performance of DDR Controllers Using Formal Verification
4:00pm - 4:15pm PDT Tuesday, July 28 Seaside Ballroom A
Design
EDA
Engineering Poster
Zero‑Glitch Confidence: An End‑to‑End Static, Formal & Simulation Methodology
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Sessions
Research Manuscript
Foundations and Frontiers: Bridging Traditional EDA and Generative AI
10:30am - 12:30pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Research Manuscript
Self-Driving EDA: Agents, Benchmarks, and Evolving Toolchains
1:30pm - 3:00pm PDT Monday, July 27 Mtg Room 101A
AI
AI2-I. AI/ML Algorithms and Models
Research Special Session
Stacked, Packed, and Fully Tested: Advanced Packaging Done Right
1:30pm - 3:00pm PDT Monday, July 27 Mtg Room 201A
Systems
Research Manuscript
Fast, Smart, and Agentic: Accelerated Verification with Fuzzing, RL, and LLMs
3:30pm - 5:30pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA2. Design Verification and Validation
Research Manuscript
Closing Integrity Faster: Physics- and Learning-Based Methods for Power, EM/IR, and Thermal
3:30pm - 5:30pm PDT Monday, July 27 Mtg Room 202AB
EDA
EDA4. Power Analysis and Optimization
Contributors
Shreyashi .
Krish Aggarwal
karam ahn
Luca Amaru
Sai Atluri
Naveen B
Aatreyi Bal
Harikrishnan Balagopal
Harikrishnan Balagopal
suresh barla
Vikram Bhatia
Norman Chang
Yi-Hang Chen
Jie Cheng
Jimmy Cheng
Morten Christiansen
zhenghao chu
minjae chung
Kelly Damalou
Sabya Das
Jack Deng
Mahesh Dhanekula
Sri Ganta
Tapas Govindraju
Scott Guo
Barkha Gupta
Harsh Gupta
Prateek Gupta
Suchir Gupta
Zhenze Han
Karan Hiranandani
Ming-Hui Hsieh
Kartik Iyer
Anshul Jain
Anushruti Jaiswal
Sandeep Jana
Amit Jangra
Haoliang Jiang
Muhammed Luqman Jukaku
Tianze Kan
PRATHWIKA KANNAGOLA PRAKASH
HYESUN KIM
Rajesh Kotha
Kopal Kulshreshtha
Akhilesh Kumar
MANJEET KUMAR
Raushan Kumar
Charles Kuo
Pradhosh Lakshmi Narasimhan
Isha Lale
Walter Lau Neto
haixun lian
Junjun Liang
Lang Lin
Lang Lin
Lang Lin
Ming-Chih Lin
Rodger Luo
Yujing Luo
Hongwei Ma
Raja Mahadevan
Sujyesh Aanandh Manjunthan
Felipe Marranghello
Giulia Meuli
Jacob Minz
Sukanya More
Subrata Nandy
Gung-Yu Pan
KUNSANG PARK
NAYEON PARK
Srinidhi Parshi
S R Pavitra
Pradip Prajapati
Anika Prasad
Disha Puri
Renjith R
Scott Ragon
Vivek Raheja
Chidambaram Rakkappan
Karan Rawat
Fei Ren
Roshan Roy
Shailandar Sachdeva
Sean Safarpour
Shreya Sashi
Geethu Sathees Babu
Sayandeep Sayandeep Sanyal
Sridhar Seshadri
Sharika Shaju
Ahmed Shebaita
Henry Sheng
Rakesh Shenoy
Khawja Sikander
Awantika Singh
Harvinder Singh
Ayush Sood
Vinuja Sridhar
Shatakshi Srivastava
Ravi Subramanian
Garth Sundberg
Nate Tai
Alessandro Tempia Calvino
Eleonora Testa
Patrick Vuillod
Anubhaw Xess
Wenbo Xia
Zhimin Xu
Omar Yamak
Jessica Yen
JONGWON YI
Xiaomei You
Ran Zhang
Chang Zhao
Li Zou
Li Zou
Session Chairs
Abhijeet Chakraborty
Sabya Das
Sashi Obilisetty
Vivek Tiwari
Zheng Zhao
Yervant Zorian