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The Chinese University of Hong Kong, Shenzhen
Presentations
Research Manuscript
Alphaplacer: Analog Placement Enhanced by Monte Carlo Tree Search
3:30pm - 3:42pm PDT Wednesday, July 29 Mtg Room 101B
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Research Manuscript
Diffsp: Differentiable Sequence Pair-Based Analog Placement
4:30pm - 4:42pm PDT Wednesday, July 29 Mtg Room 101B
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Research Manuscript
DSPE: An Energy-Efficient Edge Processor for Deepseek Inference with Merkletree-Based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing
11:50am - 12:03pm PDT Monday, July 27 Mtg Room 101B
AI
AI4-I. AI/ML Architecture Design
Research Manuscript
GRACE: A Ground Plane Generation and Re-Routing Aware Co-Design Engine
4:30pm - 4:42pm PDT Tuesday, July 28 Mtg Room 203AB
EDA
EDA7-II. Physical Design and Verification
Research Manuscript
Moduplace: LLM-Assisted Modular PCB Placement via Preference-Optimized Constraint Graph Generation
4:18pm - 4:30pm PDT Tuesday, July 28 Mtg Room 203AB
EDA
EDA7-II. Physical Design and Verification
Research Manuscript
PCBgen3D: A Self-Correcting Graph-Based MLLM Framework for Automated PCB 3D Models Generation
1:30pm - 1:42pm PDT Monday, July 27 Mtg Room 101A
AI
AI2-I. AI/ML Algorithms and Models
Contributors
Tinghuan Chen
Zhaohai Di
Zuxun Duan
Beichen Li
Yapeng Li
Yanshi Liang
Jindong Tu
Yihe Wang
Tongkai Wu
Baohui Xie
Yanqing Xu