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University of California, Berkeley
Presentations
Research Manuscript
Hierarchical Boundary Recovery: Overcoming Synthesis Obscurity via SAT Sweeping
12:16pm - 12:30pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Research Manuscript
L2L: Logic to Layout Exploration of Standard Cell Library Design
1:55pm - 2:08pm PDT Tuesday, July 28 Mtg Room 101B
EDA
EDA8. Design for Manufacturability and Reliability
Research Manuscript
Shared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen Synthesis
4:36pm - 4:50pm PDT Tuesday, July 28 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Work in Progress
SPEEDY: Single-Step Reinforcement Learning Framework for Efficient Analog Circuit Sizing Optimization
6:45pm - 6:46pm PDT Monday, July 27 Exhibit Hall
Contributors
Matteo Guarrera
Alan Mishchenko
Rikky Muller
Pierluigi Nuzzo
Alberto Sangiovanni-Vincentelli
Chun-Yen Wu
Chun-Yen Yao