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National Center of Technology Innovation for EDA
Presentations
Research Manuscript
A Levelized Load-Balanced and Structure-Adaptive GPU LU Factorization Method for Circuit Simulation
2:34pm - 2:47pm PDT Monday, July 27 Mtg Room 202AB
EDA
EDA6. Analog CAD, Simulation, Verification and Test
Research Manuscript
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
3:30pm - 3:42pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Cupilot: A Strategy-Coordinated Multi-Agent Framework for CUDA Kernel Evolution
1:42pm - 1:55pm PDT Monday, July 27 Mtg Room 101A
AI
AI2-I. AI/ML Algorithms and Models
Research Manuscript
DIA-CIM: A Dynamic Iterative Aggregation Graph Neural Network and Its Hardware Co-Design for Energy-Efficient Graph Processing
11:10am - 11:23am PDT Monday, July 27 Mtg Room 203AB
Design
DES2A. In-memory and Near-memory Computing Circuits
Research Manuscript
Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
11:18am - 11:30am PDT Wednesday, July 29 Mtg Room 202AB
EDA
EDA2. Design Verification and Validation
Contributors
shaokai ren
Yongtian Ren
Mengxia Tao
Jun Yang
mengli zhang
Tianhao Zhao