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Siemens
Presentations
Engineering Poster
A Novel Design Approach for Optimized EMC and Thermal Performance in Next-Generation Automotive Applications
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
A Novel Methodology for Automated LVS Rule Deck Verification: Truth Table and Device Extraction Qualification
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
A Unified QA Framework for Intel Library Validation Using Siemens Solido Crosscheck
2:30pm - 2:45pm PDT Monday, July 27 Seaside Ballroom B
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Accelerating DFT Verification and Enhancing Debuggability Using Veloce-Based Full Chip Gate-Level Emulation
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Late Breaking Results
Student
Work in Progress
Accelerating Functional Fault Grading for Flash and DRAM Designs
6:32pm - 6:33pm PDT Monday, July 27 Exhibit Hall
Student
Engineering Poster
Accelerating Memory Cache Verification with AI-Powered Batch Flow Methodology
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Accurate Characterization Methodology for Combo-IO Design with Concurrent Switching Outputs for Precise Power Analysis at SoC
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Achieving "zero Defect" Quality in Automotive Ethernet Solutions with AI-Accelerated Trimming & Verification
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Adaptive AI and Additive AI Techniques for High-Sigma Standard Cell Verification
1:45pm - 2:00pm PDT Monday, July 27 Seaside Ballroom B
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Advancing Silicon Lifecycle Management with Embedded Trace
4:00pm - 4:15pm PDT Monday, July 27 Seaside Ballroom B
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
AI-Accelerated Optimization Flow for Robust Analog and Mixed-Signal Circuit Design Against Process Variation
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
AI-Accelerated Signoff Verification and Glitch Analysis for Single and Multibit Level Shifters
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
An Optimized Full-Chip Analog Mixed-Signal (AMS) Verification Approach for PVT Calibration in FPGA Systems
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Research Manuscript
BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis
3:42pm - 3:54pm PDT Monday, July 27 Mtg Room 202AB
EDA
EDA4. Power Analysis and Optimization
Engineering Poster
Boosting IP Quality and Productivity Through Ipdelta Profile-Driven Change Detection
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Breaking the Simulation Wall – Practical Acceleration for Pre-Silicon Validation
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Bridging Analog Fidelity and Digital Performance in Chiplet Interface Mixed-Signal IP Verification
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Comprehensive Physical Verification Approach for Heterogeneous 2.5/3D Integration
10:30am - 10:45am PDT Monday, July 27 Seaside RM 7
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Comprehensive SoC Power System Verification Using Optimized Mixed-Signal Verification Methodology
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Early Antenna Analysis for IC Design: A Shift-Left Approach to Improve Productivity and Signoff Quality
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Enhancing the Robustness of Impinj RAIN RFID Design Through the Application of AI-Powered Process Flow
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
From Bottleneck to Breakthrough! Accelerating Circuit Verification Beyond Expectations
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
DAC Pavilion Panel
From RTL to Reality: Building Security into the Silicon Lifecycle
2:00pm - 2:45pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
TechTalk
From Tools to Agents: Realizing Fully Autonomous EDA Workflows
11:15am - 12:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Engineering Poster
Google's Faster and Earlier Chip Finishing with Seamless Power Grid Enhancement Integration
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Hierarchical Functional Fault Grading with Auto-Identification of Observation Points for Faster Fault Coverage Closer in Complex SoCs
11:45am - 12:00pm PDT Tuesday, July 28 Seaside RM 7
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Identifying Weakest Links: A Cell Scoring Metric for Robust Design in Advanced Nodes
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
DAC Pavilion Panel
Is EDA AI Delivering on Its ROI Promise?
4:00pm - 4:45pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
Late Breaking Results
Late Breaking Results: Nano-TSV Assignment for Backside Power Delivery Network Designs Considering Stress and IR-Drop Effects
6:40pm - 6:43pm PDT Monday, July 27 Exhibit Hall
Engineering Poster
Liberty-Based Profiling for IP Benchmarking
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Library PPA DTCO with Library Profiler
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Local Layout Effect Coverage Check Using Artificial Neural Network-Based Surrogate Models
1:30pm - 1:45pm PDT Wednesday, July 29 Seaside RM 7
EDA
Engineering Poster
Meeting EDA Workload Capacity Needs with AWS for Siemens' Solido Custom IC Technologies
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
New Thermal Analysis Workflow for 3DIC Designs
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Real-Time Local Layout Effects Analysis for Advanced Design Optimization
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Resistive Model-Based via Optimizatiion
5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Screening Analog Anomality for Security Vulnerability in Digitally Verified Crypto Cores
11:30am - 11:45am PDT Wednesday, July 29 Seaside Ballroom B
Design
EDA
Security
Systems
Exhibitor Forum
SIEMENS: FPGA-Based Prototyping Like You Wouldn't Believe
12:00pm - 12:30pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor
Exhibitor Forum
SIEMENS: Intelligence Between the Runs: Agentic AI for Feedback-Driven Verification
12:00pm - 12:30pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor
Engineering Poster
Unifying Pre- and Post-Silicon Software Validation Through Modeling
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Sessions
Research Manuscript
From SAT to IC3: Modern Proof Techniques for Hardware Correctness
10:30am - 12:30pm PDT Wednesday, July 29 Mtg Room 202AB
EDA
EDA2. Design Verification and Validation
Contributors
Jayne Alexander
Mohamed Alimam
Ajaj Ansari
Harshit Arora
Mohamed Atoua
Artur Babayan
David Chao
Kai-Yuan Chao
Kai-Yuan Chao
Vivek Chickermane
Manik Chugh
Abdelrahman Darwish
Arman Davtyan
Gaurav Deshpande
Jeff Dyck
Baher El Sayed
Matthieu Fillaud
Harry Foster
Gaurav Goel
Arun Gogineni
Arun Gogineni
Amit Gupta
Devdatt Haldipur
Nermeen Hossam
Lih-Jen Hou
Juergen Jaeger
Sara Khalaf
Chanjin Kim
Inhwan Kim
Abhi Kolpekwar
Saurabh Kulkarni
Ajay Kumar
Ahyoung Kwak
Geonbeom Kwon
Subramanian Lalgudi
Heng Lan Lau
Jeongjun Lee
Justin Lee
Sungyoun Lee
YuLing Lin
Neel Natekar
Mat O'Donnell
Anish Padhi
SIDDHARTH RAVIKUMAR
Gabriel Rojas
Ahmed Saleh
Connor Schentag
Basma Serry
Kesmat Shahin
Sanghyeon Shin
Smitha Shivaji Kamathi
Siddharth Singh
Niranjan Sitapure
Saurabh Srivastava
Esraa Swillam
Anahit Unanyan
Ray Valencia
Mike Walsh
Sungyun Yoo
Euisang Yoon
Mingyong Yu
Marcel Zak
Session Chairs
Jeff Dyck