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Marvell
Presentations
Engineering Poster
Automated 3Dblox File Generation: Enabling Extremely Rapid Solution Exploration by Streamlining Thermal and IR Analysis of 3D SOICs
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Early DEF-Based Hierarchical Power Grid Shorts Analysis
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Presentation
Physical Signoff at Scale: Tackling TSV, Interposer, and ESD in 3DIC Systems
10:45am - 11:00am PDT Monday, July 27 Seaside RM 7
Chiplet
EDA
Engineering Presentation
Scalable Verification Methodology for Stacked 3D Chiplet-Based Designs Using SIP Flow
11:06am - 11:24am PDT Monday, July 27 Seaside Ballroom B
AI
EDA
Systems
Engineering Special Session
The Next Decade of Semiconductors And Transformation Through Industry, Academia, and Government
1:30pm - 3:00pm PDT Wednesday, July 29 Seaside Ballroom B
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
The Power Grid Reuse Process
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Engineering Poster
Track Analyzer + Visualizer
3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Sessions
Engineering Presentation
Serving Hot 3D-IC on Clean and Cool Plates
10:30am - 12:00pm PDT Monday, July 27 Seaside RM 7
Chiplet
EDA
Research Manuscript
Architecting the Future: Cross-Layer Breakthroughs in Compute and Memory
3:30pm - 5:30pm PDT Monday, July 27 Mtg Room 203AB
Design
DES4. Digital and Analog Circuits
Research Manuscript
RM Poster Session Three
5:30pm - 6:00pm PDT Monday, July 27
AI2-I. AI/ML Algorithms and Models
Design
DES4. Digital and Analog Circuits; Design
DES1-I. SoC
Heterogeneous
and Reconfigurable Architectures; EDA
EDA4. Power Analysis and Optimization; EDA
EDA2. Design Verification and Validation; Security
SEC4. Embedded and Cross-Layer Security; AI
AI1. AI/ML Frontiers for Hardware Design; AI
Engineering Presentation
Life at the Edge: No Faults and Perfect Timing
10:30am - 12:00pm PDT Tuesday, July 28 Seaside RM 7
EDA
Security
Contributors
Samer Akiki
Mohannad Alshawi
Zach Baldwin
Kazin Blacklow
Justin Conklin
Greg Ford
Sanghmitra Jha
Nitin Nakirekanti
Nitin Navale
Chetan Arvind Patil
Yamini Ravishankar
Nagaraj Shirali
John Sweeney
Qi Wang
Mark Westvold
Session Chairs
Patricia Fong
Tim Helvey
Zisong Wang