Close

Organization

<
NVIDIA
Presentations
Research Special Session
Advances in AI-Driven Hardware Code Generation: Insights from the Comprehensive Verilog Design Problems Benchmark
3:30pm - 4:00pm PDT Monday, July 27 Mtg Room 201A
AI
Work in Progress
Agentic AI for Chip Design and Verification: Results and Limitations from CVDP
5:13pm - 5:14pm PDT Monday, July 27 Exhibit Hall
DAC Pavilion Panel
Agentic AI in EDA: Who's in Control?
4:00pm - 4:45pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
Welcome Address
AI Supercomputing Meets EDA: Accelerating the Future of Chip and System Design
5:00pm - 5:45pm PDT Sunday, July 26 Mtg Room 104B
AI
EDA
Research Manuscript
Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC
2:08pm - 2:21pm PDT Monday, July 27 Mtg Room 101A
AI
AI2-I. AI/ML Algorithms and Models
Research Panel
Bridging Quantum, AI, and EDA: The Next Frontier of Design Automation
10:30am - 12:30pm PDT Wednesday, July 29 Mtg Room 104A
Design
Engineering Poster
First-Time-Right Power Analysis: Data-Driven Test Selection Through Real-Time Validation of Clocks, Gating and Traffic-Dependent Metrics
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
TechTalk
From Tools to Agents: Realizing Fully Autonomous EDA Workflows
11:15am - 12:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Research Manuscript
Galaxydit: Efficient Video Generation with Guidance Alignment and Adaptive Proxy in Diffusion Transformers
2:47pm - 3:00pm PDT Monday, July 27 Mtg Room 101B
AI
AI3-I. AI/ML Application and Infrastructure
Engineering Poster
Handling Timing Loops Across Non-Resettable Flops in a Synchronous Resets Design: An Innovative Technique
5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Research Manuscript
Hyspecpro: Scalable Hypergraph Partitioning via Spectral Projection Optimization
5:18pm - 5:30pm PDT Tuesday, July 28 Mtg Room 203AB
EDA
EDA7-II. Physical Design and Verification
DAC Pavilion Panel
Is EDA AI Delivering on Its ROI Promise?
4:00pm - 4:45pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor
Late Breaking Results
Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond
6:01pm - 6:04pm PDT Monday, July 27 Exhibit Hall
Research Manuscript
LATTE: Legality-Assured Differentiable Timing-Driven Detailed Placement
3:30pm - 3:42pm PDT Wednesday, July 29 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
LRTA: Routability-Driven 3D-Aware Track Assignment with Layer Reassignment
4:54pm - 5:06pm PDT Tuesday, July 28 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Engineering Presentation
Multi-Level Intelligent Waveform Orchestration: Specification-Aware Framework for Eliminating Storage-Debug Tradeoffs
11:15am - 11:30am PDT Tuesday, July 28 Seaside Ballroom A
AI
Design
EDA
Research Manuscript
Optimizing Dynamic-Shape Neural Networks: A Unified Approach to Adaptive Tuning
5:16pm - 5:30pm PDT Wednesday, July 29 Mtg Room 201B
AI
AI5-II. AI/ML System and Platform Design
Research Manuscript
PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
10:30am - 10:42am PDT Wednesday, July 29 Mtg Room 202AB
EDA
EDA2. Design Verification and Validation
Research Manuscript
Pushing the Limits of Inverse Lithography with Generative Reinforcement Learning
2:47pm - 3:00pm PDT Tuesday, July 28 Mtg Room 202AB
EDA
EDA8. Design for Manufacturability and Reliability
Research Manuscript
Safegen: LLM-Driven Assertion Generation and Fault Criticality Evaluation for Functional Safety
2:47pm - 3:00pm PDT Wednesday, July 29 Mtg Room 202C
EDA
EDA9. Test, Validation and Silicon Lifecycle Management
Research Manuscript
Schemacoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting
2:47pm - 3:00pm PDT Monday, July 27 Mtg Room 101A
AI
AI2-I. AI/ML Algorithms and Models
Engineering Poster Gladiator
Sigma Profiling: Profiling Solution for Power Integrity Signoff
2:22pm - 2:33pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Research Manuscript
TOPCELL: Topology Optimization of Standard Cell via LLMs
11:10am - 11:23am PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Special Session
Toward Agentic Solutions for DRC Challenges in Digital VLSI Design
5:00pm - 5:30pm PDT Monday, July 27 Mtg Room 201A
AI
Work in Progress
Will AI Mess my RTL? A Snapshot-Based Approach to Verifying AI-Written RTL
5:23pm - 5:24pm PDT Monday, July 27 Exhibit Hall
Sessions
Research Special Session
When Generative AI Meets Analog Design: A Journey From Agent to Expert?
10:30am - 12:30pm PDT Monday, July 27 Mtg Room 201A
AI
Research Manuscript
The Dawn of the Computational Frontier: Pioneering Devices and Interconnects Empowering Memory-Centric, AI-Scale Systems
10:30am - 12:30pm PDT Monday, July 27 Mtg Room 202C
Design
DES5. Emerging Device and Interconnect Technologies
Research Manuscript
Differentiable Dreams: GPU-Powered Litho Gets Its Gradient Groove Back
1:30pm - 3:00pm PDT Tuesday, July 28 Mtg Room 202AB
EDA
EDA8. Design for Manufacturability and Reliability
Research Manuscript
RM Poster Session Five
3:00pm - 3:30pm PDT Tuesday, July 28
Quantum
DES3. Emerging Models of Computation
EDA
EDA8. Design for Manufacturability and Reliability; Design
DES6. Quantum Computing; Chiplet
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package; Systems
SYS5. Embedded Memory and Storage Systems; AI
AI3-II. AI/ML Application and Infrastructure; Design
Research Manuscript
Orchestrating LLM Systems at Scale: Heterogeneity, Memory, and Throughput
3:30pm - 5:30pm PDT Tuesday, July 28 Mtg Room 101B
AI
AI5-I. AI/ML System and Platform Design
Research Manuscript
From Analog to 3D Packaging: Enabling Routing and Clocking for Next-Generation Systems
3:30pm - 5:30pm PDT Tuesday, July 28 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
RM Poster Session Six
5:30pm - 6:00pm PDT Tuesday, July 28
EDA7-II. Physical Design and Verification
Design
EDA5. RTL/Logic Level and High-level Synthesis; Security
DES1-I. SoC
Heterogeneous
and Reconfigurable Architectures; AI
AI2-II. AI/ML Algorithms and Models; EDA
EDA7-I. Physical Design and Verification; AI
AI5-I. AI/ML System and Platform Design; EDA
SEC2. Hardware Security: Primitives
Architecture
Design & Test; EDA
Research Manuscript
Placing the Future Beyond Cells: From Transistors to 3D Integration
3:30pm - 5:30pm PDT Wednesday, July 29 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
RM Poster Session Nine
5:30pm - 6:00pm PDT Wednesday, July 29
Systems
EDA6. Analog CAD
Simulation
Verification and Test; Design
DES1-I. SoC
Heterogeneous
and Reconfigurable Architectures; AI
AI2-II. AI/ML Algorithms and Models; EDA
EDA7-I. Physical Design and Verification; AI
SEC2. Hardware Security: Primitives
Architecture
SYS5. Embedded Memory and Storage Systems; EDA
AI5-II. AI/ML System and Platform Design; Security
Design & Test
Contributors
Abhishek Akkur
Neil Ashton
Chen-Chia Chang
Emmanuel Chao
Arjun Chaudhuri
Timothy Costa
Steve Dai
Girish Deshpande
Chia-Tung Ho
Ben Keller
Brucek Khailany
RONGJIAN LIANG
Wen-Hao Liu
Yi-Chen Lu
Vishal Malik
Igor Markov
Igor Markov
Marcelo Orenes-Vera
Nathaniel Pinckney
Haoxing Ren
Santosh Santosh
Vinoth Selvan
Rohit Kumar Sinha
Anusha Vemuri
Da Yang
Donglin Yang
Haoyu Yang
Session Chairs
Yonggan Fu
Kishor Kunal
Yaguang Li
Rongjian Liang
Haoyu Yang
Zhongzhi Yu