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Presentations
Research Manuscript
Advancing Macro Placement: Integrating Proven Design Practices with Reinforcement Learning
5:06pm - 5:18pm PDT Wednesday, July 29 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
Transsyn: Scalable, Area-Oriented Transistor Network Synthesis via Cut-Based Mapper with SAT-Based Refinement
4:23pm - 4:36pm PDT Tuesday, July 28 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Sessions
Research Manuscript
Silicon Whisperers: When LLMs Learn to Speak RTL
3:30pm - 5:30pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Contributors
Chia-Wei Chen
Tai-Yu Cheng
Bo-Jiun Hsu
Wei-Min Hsu
Heng-Liang Huang
Hsuan-Ming Huang
Kun-Chin Huang
Hsin-Chuan Kuo
Yi-Ying Liao
Jiun-Cheng Tsai
Sheng-Tai Tseng
Tailai Tung
Chun-Chih Yang
Jen-Hang Yang
Session Chairs
Tailai Tung