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City University of Hong Kong
Presentations
Research Manuscript
Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
3:42pm - 3:54pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA2. Design Verification and Validation
Research Manuscript
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
3:30pm - 3:42pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
5:18pm - 5:30pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Circuitdiff: Bridging Netlist Knowledge with RTL Based on Graph Denoising Diffusion
11:36am - 11:50am PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
Freebit: Unleashing the Performance Potential of Low-Bit LLMs Through PIM
1:30pm - 1:42pm PDT Wednesday, July 29 Mtg Room 203AB
Design
DES2B-II. In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
Freezone: An On-Device Out-of-Order Writes Reordering Scheme for Consumer Zoned Storage
1:30pm - 1:42pm PDT Tuesday, July 28 Mtg Room 203C
Systems
SYS5. Embedded Memory and Storage Systems
Research Manuscript
HYPER-CIM: Hierarchical Predictive Exploration and Realizable Design Flow for High-Efficient Digital CIM
10:43am - 10:56am PDT Monday, July 27 Mtg Room 203AB
Design
DES2A. In-memory and Near-memory Computing Circuits
Research Manuscript
In-Memory ADC-Based Nonlinear Activation Quantization for Efficient In-Memory Computing
2:34pm - 2:47pm PDT Wednesday, July 29 Mtg Room 203AB
Design
DES2B-II. In-memory and Near-memory Computing Architectures, Applications and Systems
Research Manuscript
Insights from Verification: Training a Verilog Generation LLM Using Reinforcement Learning with Testbench Feedback
11:10am - 11:23am PDT Monday, July 27 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Research Manuscript
On-Demand Multi-Task Sparsity for Efficient Large-Model Deployment on Edge Devices
3:42pm - 3:54pm PDT Tuesday, July 28 Mtg Room 101A
AI
AI2-II. AI/ML Algorithms and Models
Research Manuscript
Paretopilot: Global Optimization Reasoning on HLS Design Space Exploration with LLMs
1:55pm - 2:08pm PDT Monday, July 27 Mtg Room 101A
AI
AI2-I. AI/ML Algorithms and Models
Research Manuscript
Uvmarvel: an Automated LLM-Aided UVM Machine for Subsystem-Level RTL Verification
4:06pm - 4:18pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA2. Design Verification and Validation
Research Manuscript
ZK-Tracer: A High-Performance Heterogeneous Accelerator for Zero-Knowledge VM Trace Generation
3:54pm - 4:06pm PDT Wednesday, July 29 Mtg Room 203AB
Design
DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures
Contributors
Arindam Basu
Zichong Deng
Shuai Dong
Nan Guan
Haibo Hu
Lianming Huang
Mengyang MA
Hongyang Shang
Ning Wang
Shangyu Wu
Junyi Yang
Bingkun Yao
Biyan Zhou