Contributors
A
Engineering Poster Mixed Transistor Design Closure
Research Manuscript ARC-SRAM: A Memory Subarray with Local Addressing and Reduced Access Energy
Engineering Poster Xchip: A Guardrailed Agentic Gen-AI Front-End Flow from Intent to GDSII
Engineering Presentation Design Spec to Die-Size Estimation Using ML Based Framework for Automotive SoCs
Engineering Poster Activity Reloaded: Joules Flash Replay - A Methodology for Accurate, Delay-Based Activity Generation for Driving Optimization and Power Sign-off
Engineering Poster From Concept to PPA Confidence - Methodology for Rapid RTL Evaluation and Signoff with Joules RTL Design Studio.
Engineering Presentation Strong Foundations Lead to High Impact Gains
Engineering Poster Channel Width Optimization for IR Drop Reduction in Advanced SoCs
Engineering Special Session Role of FPGAs in Emulation and Prototyping Systems
Engineering Poster ECO Strategy for BIG DIE SOC Convergence
Engineering Special Session A Unified Agentic Architecture for Rapid Deployment of Zero-Hallucination GenAI Applications
Research Manuscript Differentiable Fill Insertion with Explicit Delay Optimization
Engineering Presentation Progress-Based Timeout Debug for Scalable SoC Verification
Research Special Session Toward Agentic Solutions for DRC Challenges in Digital VLSI Design
Research Manuscript Notsotiny: A Large, Living Benchmark for RTL Code Generation
Research Manuscript Enabling AI ASICs for Zero Knowledge Proof
Engineering Presentation Physical Signoff at Scale: Tackling TSV, Interposer, and ESD in 3DIC Systems
Research Manuscript BREW-RC: Bit-Exact Recovery of ECCs from Write Timing in ReRAM Crossbars
Research Manuscript Sparsity- and Tolerance-Aware Temporally Redundant Neural Networks
Research Manuscript Shared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen Synthesis
Research Manuscript Unlocking Automated Datapath Gating via Machine Learning Power Prediction
Engineering Poster Design Verification Automation (DVA) for PCB Signal and Power Integrity
Research Manuscript Epicell: Electro-Physical Co-Modeling for Standard Cell PPA Prediction
Engineering Poster Gladiator Agile Silicon: A Gitops-Based PD Orchestration Framework Enabling <10-Person PD Team to Deliver CPO Tapeouts
Research Manuscript RAM-CGRA: Reachability-Aware Mapping for CGRAs
Engineering Special Session AI and Multi‑die: A Reinforcing Cycle
Work in Progress Late Breaking Results: Encoding-in-Memory via Generating True Random One-Time Password
Late Breaking Results Late Breaking Results: ROAST: Reverse-Training Offset Attack on Spatial Sampling Topologies
Research Manuscript Light-Bound Transformers: Hardware-Anchored Robustness for Silicon-Photonic Computer Vision Systems
Research Manuscript RM Poster Session Two
Research Special Session Skip the Commute: Near-Memory and Near-Sensor Intelligence for Edge AI Systems
Research Special Session Co-Designed Compute Memories for Ultra-Efficient DNN Inference
Research Manuscript Beyond GPUs: Next-Generation Architectures for Modern AI Workloads
Research Manuscript LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout
Research Manuscript RM Poster Session One
Engineering Presentation From Design to Defense: Pioneering Pre-Silicon Leakage Detection for Novel ECC Crypto Core
Engineering Poster A Hybrid Simulation and Formal Verification Approach for Exhaustive Interrupt and Status Flag Verification
Engineering Poster Enhancing UVM RAL for Secure and Privileged Flash Memory Interface Verification Using Cadence AMBA VIP
Engineering Presentation In-Situ Architecture for Detecting and Mitigating Off-Chip Interface Attacks
Engineering Poster Innovative Multiplatform Framework Boosting 10BaseT Ethernet Verification for Next-Gen Automotive SoCs
Engineering Presentation No More Blind Spots: RTL Modeling of Metastability for CDC Verification
DAC Pavilion Panel Is EDA AI Delivering on Its ROI Promise?
Research Special Session Co-Designed Compute Memories for Ultra-Efficient DNN Inference
Research Manuscript Greenllm: SLO-Aware Dynamic Frequency Scaling for Energy-Efficient LLM Serving
Engineering Presentation Adaptive AI and Additive AI Techniques for High-Sigma Standard Cell Verification
Research Manuscript Sparsity- and Tolerance-Aware Temporally Redundant Neural Networks
Research Manuscript RM Poster Session Seven
B
Research Manuscript Hot Chips & Cool Models: AI Turns Up the Heat on Silicon Design
Research Manuscript RM Poster Session One
Engineering Poster ECO Strategy for BIG DIE SOC Convergence
Engineering Poster Performance Boosting DTCO Methodology for 1-to-1 Metal-Gate Pitch Ratio
Research Manuscript Vten: Tensor-Centric Verification Framework for Domain-Specific Accelerators
Research Manuscript Adaptive Spiking Neural Networks for Real-Time Multi-Object Detection Tasks
Engineering Presentation Formal Verification: Prove It. Don’t Hope It.
Research Manuscript RM Poster Session Six
Research Manuscript Structuring the Blueprint: Scalable Partitioning and Early-Stage Floorplanning
Engineering Poster A Scalable Timing Analysis and Closure Methodology for Ultra-Large Designs
Engineering Presentation Formally Validating Industry Standard BCH‑ECC/CRC Codes – A Step by Step Recipe
Engineering Poster A Compact Digital IP for FMCW Chirp Linearity Monitoring in Automotive Radar Systems
Engineering Poster An Adaptive Dynamic Power Reduction Technique for Digital Filters
Engineering Special Session Digitally Assisted Analog Techniques for Next‑Generation Data Converters, Test, and Clocking
Engineering Presentation In-Situ Architecture for Detecting and Mitigating Off-Chip Interface Attacks
Engineering Presentation No More Blind Spots: RTL Modeling of Metastability for CDC Verification
Engineering Poster Free Hand Routing- Sketch to Layout
Engineering Presentation From Design to Defense: Pioneering Pre-Silicon Leakage Detection for Novel ECC Crypto Core
Engineering Presentation Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
Late Breaking Results Late Breaking Results: Towards Low-Latency TinyML via Regularized Activation Packing
Research Manuscript RM Poster Session Eight
Engineering Poster A Compact Digital IP for FMCW Chirp Linearity Monitoring in Automotive Radar Systems
Engineering Poster An Adaptive Dynamic Power Reduction Technique for Digital Filters
Research Manuscript Agent-Per-Qubit: Automated Qubit Placement for Fault-Tolerant Quantum Computing
Exhibitor Forum CHIPAGENTS AI: AI Agent-Driven Timing Closure
Engineering Presentation A Unified QA Framework for Intel Library Validation Using Siemens Solido Crosscheck
Research Manuscript Memory That Thinks: Scalable, Reliable, and Secure Compute-in-Memory Systems
Engineering Presentation Automated Verification and Performance Analysis for Chiplets
Research Manuscript Architectures for Sparse, Adaptive, and Scalable Acceleration
Research Manuscript RM Poster Session Three
Research Special Session Making Story Worlds Feel Alive: Embedded Intelligence and Authored Agency in Themed Entertainment
Engineering Presentation Optimizing Digital SOC Designs, One Cell at a Time Using AI Transistor-Level Sizing
Research Special Session Skip the Commute: Near-Memory and Near-Sensor Intelligence for Edge AI Systems
Engineering Presentation AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
Engineering Presentation A Mixed-Domain Modeling Approach for Hatched Ground Planes in 3D Chiplet Die-to-Die Interconnect
Exhibitor Forum CHIPAGENTS AI: AI Agent-Driven Timing Closure
Engineering Special Session The Next Decade of Semiconductors And Transformation Through Industry, Academia, and Government
Research Manuscript Exploiting Movable Logical Qubits for Lattice Surgery Compilation
Research Manuscript Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding
Engineering Poster Bridging Hardware-Software Abstraction In UVM Verification
Engineering Presentation Precision in Practice: Advanced Verification Techniques for Modern Silicon
Engineering Presentation Lint-Free: A Generative AI Approach to Large Scale Autonomous RTL-Lint Correction
Engineering Presentation Multi-Agent Generative AI Pipeline for Assisting in Design Verification
Exhibitor Forum SYNOPSYS: How Silicon Startups Are Addressing the AI Memory Gap
Engineering Poster Multi-Agent Automated Formal Verification for Automative Applications
Engineering Poster ARTEMIS: Agentic AI for EDA
Engineering Poster Accelerating Full Flat EMIR Sign-Off in Multi-Billion Instance
Engineering Presentation Hardening Security of HW IPs by Verifying Their Negative Space Formally
Research Manuscript Scalable Reliability Assessment of DNNs Through Simultaneous Fault Injection
Research Manuscript ARC-SRAM: A Memory Subarray with Local Addressing and Reduced Access Energy
Engineering Presentation Optimizing Digital SOC Designs, One Cell at a Time Using AI Transistor-Level Sizing
Engineering Presentation A Soft-Microcode Engine to Power the Next Wave of Edge Intelligence
Engineering Presentation Multi-Agent Generative AI Pipeline for Assisting in Design Verification
Research Manuscript Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding
Work in Progress SPICEMixer - Netlist-Level Circuit Evolution
Engineering Poster Agentic Time-Travel Debugging for HLS Code
United States of America
Research Manuscript Stateful Embedded Fuzzing Using Peripheral-Accurate Systemc Virtual Prototypes
Engineering Special Session Role of HW Based Tools like Emulation and Prototyping in Semiconductor Design Methodology
Research Manuscript Fast, Furious, and Fault-Tolerant: Accelerating the Generative Grind
Research Manuscript GREEN: Towards Scalable Energy-Efficient Workload Scheduling and Placement in the Cloud
Research Manuscript RM Poster Session Eight
Research Manuscript Shortcircuit: Alphazero-Driven Generative Circuit Design
Research Manuscript ARC-SRAM: A Memory Subarray with Local Addressing and Reduced Access Energy
Engineering Presentation Designing Power- and Area-Efficient Custom NPUs for Edge AI
Engineering Presentation Multi-Cycle Interconnect Synthesis in Small to Large Cutting Methodology
Research Manuscript RM Poster Session Eight
Research Manuscript Dropping Multiple Literals per SAT Call in IC3 Model Checking
Engineering Poster Automatic SDC Creation for Static Timing Analysis
Research Manuscript Search Smarter, Not Harder: A Scalable, High-Quality Zoned Neutral Atom Compiler
Research Special Session Local AI, Models-as-Media, and the Future of Entertainment
Research Manuscript TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
Engineering Poster Gladiator ML-Based Sigma Av–aware Switch Cell Optimization
C
Engineering Presentation Deep Reinforcement Learning Paradigm for Analog Design Automation
Engineering Presentation Efficient IR-Aware Powergrid Optimization
Engineering Poster Achieving High-Integrity Safety for 360-Degree Automotive Display Soc's RETIME-IP: A Static Analysis Approach to ASIL-D Compliance
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Research Manuscript Towards Practical Live Migration for Heterogeneous Confidential Virtual Machines
Research Manuscript FBS: Accelerating CNN Inference over RNS-CKKS with Fewer Bootstrapping Sparsity
Research Manuscript PRS: An Efficient Parallel SAT Framework
Research Manuscript Parallel Combinational Equivalence Checking via Sweeping-Based Task Scheduling
Research Manuscript RM Poster Session Nine
Research Manuscript FBS: Accelerating CNN Inference over RNS-CKKS with Fewer Bootstrapping Sparsity
Research Manuscript KERV: Kinematic-Rectified Speculative Decoding for Embodied VLA Models
China
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
Research Manuscript Autonomous Synthesis and Intelligent Optimization for Analog and RF Circuits
Research Manuscript RM Poster Session Nine
Research Manuscript Dynamic-Cost Area Recovery for Fracturable LUT-Based FPGAs
Research Manuscript Lhgstore: An In-Memory Learned Graph Storage for Fast Updates and Analytics
Research Manuscript Lhgstore: An In-Memory Learned Graph Storage for Fast Updates and Analytics
Engineering Presentation AI-Assisted EDA Tools Development
Engineering Presentation AI-Enabled EDA Cloud Infrastructure and Design Optimization for Next-Generation Semiconductor Design
Research Manuscript CARAMEL: Boosting Device Utilization in Control Flow Auditing
Research Manuscript Vten: Tensor-Centric Verification Framework for Domain-Specific Accelerators
DAC Pavilion Panel What Are VCs Looking for at DAC?
Research Manuscript RM Poster Session Seven
Research Manuscript RM Poster Session Four
Research Manuscript Silicon Under Siege: Hardware-Rooted Attacks and Defenses in Modern SoCs
Research Manuscript RM Poster Session Eight
Engineering Presentation AI-Enabled EDA Cloud Infrastructure and Design Optimization for Next-Generation Semiconductor Design
Engineering Presentation Static Verification: The Sentinel Guarding RTL Integrity
Engineering Poster Solving Memory Subsystem Verification Challenges for Multi-Instance Designs
Engineering Poster Novel Approach to Signoff Large MRAM Memory IP Using Hierarchical Flow
Engineering Poster A Simple and Predictable Solution for Early Full-Chip LVS Convergence
Engineering Presentation Optimizing Reliability EM Sign-Off for 2nm Mobile SoCs
Research Manuscript Ihyperg: Incremental Hypergraph Partitioning on GPU
Research Special Session Toward Agentic Solutions for DRC Challenges in Digital VLSI Design
Research Manuscript Ihyperg: Incremental Hypergraph Partitioning on GPU
Research Manuscript Targeted Bit-Flip Attacks on LLM-Based Agents
Research Manuscript PRISM: Priority Aware Shared Scale Microscaling Format for 4-Bit Quantization
Engineering Presentation From Design to Defense: Pioneering Pre-Silicon Leakage Detection for Novel ECC Crypto Core
Late Breaking Results Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond
Engineering Poster Gladiator Multi Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN Model
Engineering Presentation Accurate Impact Modeling for Threshold Voltage Mismatch of Transistors in Same Chip
Research Manuscript Active Memory: Breaking the Data Movement Wall with Cognitive Storage
Research Manuscript CPA-BNN: A Secure and Efficient CIM and PUF Architecture for BNN Accelerator
Late Breaking Results Late Breaking Results: 3D Analytical Placement with Smoothed Multi-Die Wirelength Model
Late Breaking Results Late Breaking Results: A Unified Analytical Framework for MBFF Clustering and Placement for Timing, Power, and Area Co-Optimization
Late Breaking Results Late Breaking Results: Nano-TSV Assignment for Backside Power Delivery Network Designs Considering Stress and IR-Drop Effects
Late Breaking Results Late Breaking Results: Novel Qubit Mapping for Two-Dimensional Trapped-Ion Quantum Computing Systems
Research Manuscript Adaptive Read Retry Table Extension for Enhanced Data Reliability in 3D NAND Flash Memory
Research Manuscript Flashhd: A Flash-Based In-Storage Hyperdimensional Computing Framework for Hierarchical Sequence Matching
Research Manuscript RM Poster Session Nine
Engineering Presentation Custom Implementation of High-Speed Digital Blocks Using Virtuoso Studio
Engineering Poster Gladiator Sigma Profiling: Profiling Solution for Power Integrity Signoff
Research Manuscript Inferweave: Efficient LLM Inference on the MT-3000 Processor
Research Manuscript TOPCELL: Topology Optimization of Standard Cell via LLMs
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
Research Manuscript Fast, Smart, and Agentic: Accelerated Verification with Fuzzing, RL, and LLMs
Research Manuscript GREEN: Towards Scalable Energy-Efficient Workload Scheduling and Placement in the Cloud
Research Manuscript RM Poster Session Three
Research Manuscript Schemacoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting
Research Manuscript LRTA: Routability-Driven 3D-Aware Track Assignment with Layer Reassignment
Late Breaking Results Late Breaking Results: 3D Analytical Placement with Smoothed Multi-Die Wirelength Model
Research Manuscript Amoeba: Runtime Tensor Parallel Transformation for LLM Inference Services
Hong Kong
Research Manuscript AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning
Research Manuscript Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells
Research Manuscript DRCGen: A Controllable DRC Violation Case Generator with Cross-PDK Transferability for Rule-Deck and Tool Validation
Late Breaking Results Late Breaking Results: 3D Analytical Placement with Smoothed Multi-Die Wirelength Model
Research Manuscript Etherssd: An In-Storage Ethereum Analytics Platform with Minimized I/O and Authentication Overhead
Research Manuscript Freebit: Unleashing the Performance Potential of Low-Bit LLMs Through PIM
Research Manuscript PIMGRAG: A Heterogeneous PIM Architecture for Graph-Based Retrieval-Augmented Generation
Research Manuscript SpecANNS: Accelerating Graph-Based Approximate Nearest Neighbor Search with Speculative In-Storage Computing
Research Manuscript TierANNS: Scalable Graph-Based ANNS with CXL-Enabled Tiered Data Placement
Research Manuscript Hero: Adaptive Orchestration of Retrieval-Augmented Generation on Heterogeneous Mobile SoC
Research Manuscript KERV: Kinematic-Rectified Speculative Decoding for Embodied VLA Models
Research Manuscript Cupilot: A Strategy-Coordinated Multi-Agent Framework for CUDA Kernel Evolution
Research Manuscript Shortcircuit: Alphazero-Driven Generative Circuit Design
Research Manuscript Onyx: Efficient Transaction Processing with Real Processing-in-Memory Prototypes
Research Manuscript Beyond Exact: Tight WCET Analysis of GPU Kernels with Branch Divergence
Research Manuscript Freebit: Unleashing the Performance Potential of Low-Bit LLMs Through PIM
Research Manuscript Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells
Late Breaking Results Late Breaking Results: A Fully Differentiable Rectilinear Minimum Spanning Tree Wirelength Model for Global Placement
Late Breaking Results Late Breaking Results: Merge-Aware Placement and DP-Based Wave Propagation Routing for Scalable Flip-FET Cell Layout Synthesis
Research Manuscript BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs
Research Manuscript Design Technology Co-Optimization for Network on Chip in High Performance CPUs at 3nm Node Using Monolithic 3D and Backside Interconnect Technologies
Research Manuscript Flexicts: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs
Research Manuscript Flowplace: Flow Matching for Chip Placement
Research Manuscript How Can Reinforcement Learning Achieve Expert-Level Placement?
Research Manuscript Parallel Combinational Equivalence Checking via Sweeping-Based Task Scheduling
Research Manuscript Energyhdc: Intermittent Hyperdimensional Inference on Energy-Harvesting IoT
Research Manuscript RM Poster Session Two
Research Manuscript Streamlining Silicon: From Real-Time Scheduling to Efficient GPU Execution
Research Manuscript Alphaplacer: Analog Placement Enhanced by Monte Carlo Tree Search
Research Manuscript Diffsp: Differentiable Sequence Pair-Based Analog Placement
Research Manuscript GRACE: A Ground Plane Generation and Re-Routing Aware Co-Design Engine
Research Manuscript CO-MAC: A Center-Out Ordered Stochastic MAC for Low-Latency Inference
Research Manuscript Active Memory: Breaking the Data Movement Wall with Cognitive Storage
Research Manuscript Intelligent Fetch & Match Architectures
Research Manuscript CODA: A Computation-Data Decoupled Dataflow Paradigm for DNN Computing on NPUs
Research Manuscript Efficient LLM and MoE Inference on Specialized Hardware
Research Manuscript Hero: Adaptive Orchestration of Retrieval-Augmented Generation on Heterogeneous Mobile SoC
Research Manuscript Hybrid PIM-Oriented Architecture-Dataflow Co-Design for Heterogeneous LLM Inference
Research Manuscript KERV: Kinematic-Rectified Speculative Decoding for Embodied VLA Models
Research Manuscript MIRAGE: Runtime Scheduling for Multi-Vector Image Retrieval with Hierarchical Decomposition
Research Manuscript RM Poster Session Four
Research Manuscript SpArC: Sparse Tensor Accelerator Compilation with Scheduling and Mapping
Engineering Presentation Accurate Impact Modeling for Threshold Voltage Mismatch of Transistors in Same Chip
Engineering Poster Gladiator 3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration
Engineering Presentation AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
Research Manuscript OpenSUN: An Open Platform for Exploring Scale-Up Network Systems
Research Manuscript Flashfps: Efficient Farthest Point Sampling for Large-Scale Point Clouds via Pruning and Caching
Research Manuscript PRISM: Priority Aware Shared Scale Microscaling Format for 4-Bit Quantization
Research Manuscript REFLEX: Rewrite-Free Row-Aligned Sparse Attention for Efficient LLM Execution on PIM
Engineering Special Session The Heterogeneous Future of Agentic AGI: Challenges and Opportunities!
Research Manuscript Pipegs: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning
Research Manuscript SpRDA: An Efficient Sparse Accelerator for Robotics Diffusion Model
Research Manuscript AI Graces the Cell Party: Transformers, LLMs and Zero Drama Extraction
Research Manuscript Streamlining Silicon: From Real-Time Scheduling to Efficient GPU Execution
Late Breaking Results Late Breaking Results: QUBO Approaches to Logic Equivalence Checking and Testing
Research Manuscript Pipegs: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning
Research Manuscript SpRDA: An Efficient Sparse Accelerator for Robotics Diffusion Model
Research Manuscript Knowledge-Driven Hybrid SSD Management Enhanced by Fine-Tuned LLMs
Research Manuscript PRS: An Efficient Parallel SAT Framework
Research Manuscript Parallel Combinational Equivalence Checking via Sweeping-Based Task Scheduling
China
Research Manuscript L2L: Logic to Layout Exploration of Standard Cell Library Design
Research Manuscript Optimizing Dynamic-Shape Neural Networks: A Unified Approach to Adaptive Tuning
Research Manuscript Celle: Automated Standard Cell Library Extension via Equality Saturation
Research Manuscript KL-MoE: A Hierarchical MoE Pruning Framework Exploiting KL Divergence
Engineering Presentation An Adjustable Length Compression Method for MBIST Repair Information
Research Manuscript Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge
Research Manuscript CHiRM-DSE: CodeLLM-Based Hierarchical and Rule-Mining Guided DSE for FPGA Accelerators
Research Manuscript Efficient HLS Accelerator Floorplan on Multi-Die FPGA Aided by Graph Neural Networks
Research Manuscript SpArC: Sparse Tensor Accelerator Compilation with Scheduling and Mapping
Engineering Presentation Analysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous Integration
Research Manuscript LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout
Work in Progress Lockroute: A Spatial Locking Framework for Parallel Global Routing
Research Manuscript RM Poster Session Nine
Research Special Session Toward Agentic Solutions for DRC Challenges in Digital VLSI Design
Research Manuscript Architecting the Future: Cross-Layer Breakthroughs in Compute and Memory
Research Manuscript RM Poster Session Three
Engineering Presentation Advancing Silicon Lifecycle Management with Embedded Trace
Research Manuscript CO-MAC: A Center-Out Ordered Stochastic MAC for Low-Latency Inference
Research Manuscript Differentiable Fill Insertion with Explicit Delay Optimization
Research Manuscript Test Point Insertion with ATPG-Free Self-Supervised Learning
Research Manuscript Semi-Virtual Addressing to Enhance Memory Safety on Microcontrollers
Research Manuscript SCOUT: Thermal-Aware SRAM Allocation for Real-Time DNN Tasks on Edge TPU
Work in Progress Accelerating Functional Fault Grading for Flash and DRAM Designs
Engineering Poster Gladiator LLM-Aided Cell Clustering for Placement Optimization of DRAM Peripheral Circuits
Research Manuscript Robust and Trusted AI Systems: Attacks, Defenses, and Hardware Reliability
Engineering Poster Low Power Optimization Through Fast and Accurate Time-Based Power Analysis
Engineering Poster Gladiator LLM-Aided Cell Clustering for Placement Optimization of DRAM Peripheral Circuits
Research Manuscript GTX: Graph Transformer for Parasitic Extraction on Analog Circuits
Engineering Presentation Architectural Formal Verification of Configurable Address Translation Logic for Early Bug Exposers
Engineering Poster Efficient Power Management in USB4 Routers
Engineering Presentation AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
Research Manuscript EASY-ZKP: An End-to-End FPGA-Accelerated System for Zero Knowledge Proofs
Engineering Poster Gladiator Flexible & Scalable Network Modeling for AI/HPC Network Verification
Engineering Poster Gladiator 3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration
Research Manuscript SCOUT: Thermal-Aware SRAM Allocation for Real-Time DNN Tasks on Edge TPU
DAC Pavilion Panel Agentic AI in EDA: Who's in Control?
Additional Meeting LLM Benchmarking for Chip Design – Strategic Outlook and Industry Panel
Engineering Presentation Automated System for FPGA-Based SoC Prototyping
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
Research Manuscript Quantum Circuit Synthesis Using an Exact T Library
Engineering Poster The Power Grid Reuse Process
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Presentation Enabling AI Agent Flows for Verification Triage & Debug
Engineering Special Session The Next Decade of Semiconductors And Transformation Through Industry, Academia, and Government
Engineering Special Session Model-Based Systems Engineering (MBSE) for Aerospace & Defense
Engineering Poster Agentic Time-Travel Debugging for HLS Code
Engineering Presentation Early Thermal Analysis and Silicon Correlation for Face-to-Face 3DIC Physical Design
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Research Manuscript NVLLM: A 3D NAND-Centric Architecture Enabling Edge on-Device LLM Inference
Research Manuscript Beyond Exact: Tight WCET Analysis of GPU Kernels with Branch Divergence
Research Manuscript Exploiting Dependency and Parallelism: Real-Time Scheduling and Analysis for GPU Tasks
Research Manuscript Operator-Level Acceleration for Sparse 3D Object Detection
Research Manuscript DRΛMA: Detailed Routing by a Versatile Maze Routing Algorithm
Research Manuscript CODA: A Computation-Data Decoupled Dataflow Paradigm for DNN Computing on NPUs
Engineering Presentation Automated System for FPGA-Based SoC Prototyping
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Presentation AI-Assisted EDA Tools Development
Engineering Presentation Morph-Inspect: Structural Assurance for Inserted Logic
D
Research Manuscript Beyond Exact: Tight WCET Analysis of GPU Kernels with Branch Divergence
Research Manuscript Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge
Engineering Poster A Simple and Predictable Solution for Early Full-Chip LVS Convergence
Engineering Poster Gladiator A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs
Engineering Presentation A Service-Aware Energy-Efficient DVFS Framework for System-on-Chip Architectures
Research Manuscript Enabling AI ASICs for Zero Knowledge Proof
Engineering Presentation Accurate Impact Modeling for Threshold Voltage Mismatch of Transistors in Same Chip
Work in Progress STA Accuracy Validation: A Machine Learning Approach
Engineering Poster Slack-Exploiting Load Splitting for IR-Drop Mitigation
Engineering Presentation Local Layout Effect Coverage Check Using Artificial Neural Network-Based Surrogate Models
Research Manuscript A Differentiable Approach to Task Graph Partitioning: A Case Study in RTL Simulation
Research Manuscript Ihyperg: Incremental Hypergraph Partitioning on GPU
Engineering Presentation Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
Engineering Presentation Using ML-Assisted Side-Channel Analysis in Simulation: A Case Study on AES-GCM
Engineering Poster CDG-DNN: Scalable Test Template Generation Using Adaptive Neural Architecture for Industry Class CDG Hardware Verification
Engineering Poster SELECT: Sensitivity Based Exploration and Localisation of Event-Wise Correlated Tokens for Test Generation
Engineering Presentation STEER: Simulation of Templates Engine for Efficient Resource Usage
Engineering Special Session Challenges and Solutions in the next-Generation Emulation and Prototyping Solutions
Research Manuscript Fast, Smart, and Agentic: Accelerated Verification with Fuzzing, RL, and LLMs
Engineering Special Session Role of FPGAs in Emulation and Prototyping Systems
Engineering Special Session Role of HW Based Tools like Emulation and Prototyping in Semiconductor Design Methodology
Engineering Poster Channel Width Optimization for IR Drop Reduction in Advanced SoCs
Engineering Poster Gladiator An AI-Enhanced Web-Based Real-Time Analytics & Prediction Platform for ASIC Physical Design (PD) Flows
Engineering Poster Static Timing Analysis (STA) Platform: An AI-Augmented Web System for Scalable Static Timing Analysis and Optimization
Engineering Poster TAWT: Towards Autonomous Wrapper Tuning
Research Special Session Skip the Commute: Near-Memory and Near-Sensor Intelligence for Edge AI Systems
Engineering Poster ARTEMIS: Agentic AI for EDA
Engineering Poster Advanced Automation for DC Die Generation and Verification
Engineering Presentation Comprehensive Physical Verification Approach for Heterogeneous 2.5/3D Integration
Research Manuscript CARAMEL: Boosting Device Utilization in Control Flow Auditing
Engineering Presentation BIMEM-RAG: Reinforced Dual Memory Retrieval with Bidirectional Reasoning for RTL Synthesis and Summarization
Engineering Poster Gladiator Cost-Based Partial Subgraph Matching for Circuit Pattern Recognition
Engineering Presentation Graph Isomorphism for Explainable Transistor-Level Circuit Comparison
Research Manuscript Sparsity- and Tolerance-Aware Temporally Redundant Neural Networks
Engineering Poster Efficient Power Management in USB4 Routers
Research Manuscript Stone-Skimming: Attacking Big-Data Analytics Applications with Page Table Walk
Research Manuscript WSC-Cost: An Accurate Cost Modeling Framework for Wafer-Scale Chips
Research Manuscript Marlin: I/O-Efficient Prefix KV Cache Retrieval for Long-Prefix LLM Serving
Research Manuscript FBS: Accelerating CNN Inference over RNS-CKKS with Fewer Bootstrapping Sparsity
Research Manuscript Stone-Skimming: Attacking Big-Data Analytics Applications with Page Table Walk
Engineering Poster Xchip: A Guardrailed Agentic Gen-AI Front-End Flow from Intent to GDSII
China
Engineering Presentation Multi-Agent Generative AI Pipeline for Assisting in Design Verification
Engineering Poster Gladiator Sigma Profiling: Profiling Solution for Power Integrity Signoff
Engineering Presentation Modeling and Optimization of Power MOSFET Device Layouts with Optislang Tool
Research Manuscript Enabling AI ASICs for Zero Knowledge Proof
Additional Meeting IEEE 2416 Working Group Meeting: Kickoff for Next Revision
Engineering Presentation Efficient Power Modeling of Multi-Domain Clock Gating Circuits
Research Manuscript Predictable Precision: Resilience and Timing in the Era of AI
Engineering Presentation Automated Validation of Liberty Models
Engineering Poster Mixed Transistor Design Closure
Research Manuscript LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout
Research Manuscript Pillarsparse: Rethinking Unstructured Sparse Formats for Tensor Cores
Late Breaking Results Late Breaking Results: "describing" Your Way to a Functional Microfluidic Chip
Engineering Poster Automatic SDC Creation for Static Timing Analysis
Research Manuscript Flowplace: Flow Matching for Chip Placement
Work in Progress Etch-Vigen: A Video Generation Model for Etching Simulation
Engineering Poster Accelerating IR and Timing Convergence with Revolutionary IR-ECO
Research Manuscript NVLLM: A 3D NAND-Centric Architecture Enabling Edge on-Device LLM Inference
Research Manuscript COLA: Enabling Low-Latency Reads for Flash-Based SSDs via Code Length Adaptation
Engineering Poster Novel Approach to Signoff Large MRAM Memory IP Using Hierarchical Flow
Research Manuscript Raise the Shields: A Modular RISC-V Extension for Post Quantum Cryptography
Research Manuscript Intelligent Fetch & Match Architectures
Research Manuscript RM Poster Session Two
Research Manuscript Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
Research Manuscript FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration
Research Manuscript Harnessing the Noise: p-Bits, ZKPs, and Resilient AI
Research Manuscript PHAROS: Pipelined Heterogeneous Accelerators for Real-Time Safety-Critical Systems With Deadline Compliance
Research Manuscript RM Poster Session Nine
Engineering Poster Design Rule Checking for Rigid-Flex PCB
Engineering Presentation Optimizing Digital SOC Designs, One Cell at a Time Using AI Transistor-Level Sizing
Engineering Poster Hierarchical IP Block Resizing on the Fly
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
DAC Pavilion Panel Is EDA AI Delivering on Its ROI Promise?
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Research Manuscript Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
Research Manuscript NIAQ: Adaptive Non-Ideality-Aware Qubit Readout for Long-Term Accuracy
Research Manuscript Freebit: Unleashing the Performance Potential of Low-Bit LLMs Through PIM
Research Manuscript PRISM: Dynamic Primitive-Based Forecasting for Large-Scale GPU Cluster Workloads
Research Manuscript Parallel Combinational Equivalence Checking Through Factored Form Sharing
Research Manuscript GRACE: A Ground Plane Generation and Re-Routing Aware Co-Design Engine
Research Manuscript ARC-SRAM: A Memory Subarray with Local Addressing and Reduced Access Energy
Engineering Presentation Modeling and Optimization of Power MOSFET Device Layouts with Optislang Tool
Engineering Presentation Efficient Power Modeling of Multi-Domain Clock Gating Circuits
Engineering Special Session Gaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect?
Engineering Presentation Architectural Coverage Analysis and ML-Based Automated-Test Generation
Research Manuscript From SAT to IC3: Modern Proof Techniques for Hardware Correctness
DAC Pavilion Panel Is EDA AI Delivering on Its ROI Promise?
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Research Special Session Co-Designed Compute Memories for Ultra-Efficient DNN Inference
Engineering Presentation Comprehensive Physical Verification Approach for Heterogeneous 2.5/3D Integration
Engineering Poster Design Verification Automation (DVA) for PCB Signal and Power Integrity
Engineering Presentation AI-Assisted EDA Tools Development
Engineering Presentation Enabling AI Agent Flows for Verification Triage & Debug
Engineering Poster FPGA-to-ASIC Conversion via Hierarchical Wrapping
Engineering Presentation Morph-Inspect: Structural Assurance for Inserted Logic
Research Manuscript Generative AI and Graph-Based Learning for Next-Gen Circuit & Device Simulation
Research Manuscript RM Poster Session Two
Engineering Poster Gladiator Agile Silicon: A Gitops-Based PD Orchestration Framework Enabling <10-Person PD Team to Deliver CPO Tapeouts
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Research Manuscript RM Poster Session Eight
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Research Manuscript Hierarchical Boundary Recovery: Overcoming Synthesis Obscurity via SAT Sweeping
Research Manuscript Marlin: I/O-Efficient Prefix KV Cache Retrieval for Long-Prefix LLM Serving
China
Research Manuscript Parallelizing Complementary Approximate Reachability
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Research Manuscript Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
Research Manuscript The Edge-Lord Chronicles: Tiny Gestures, Big LLMs, and Cluster Chaos
Research Manuscript PLONK-Hammer:breaking Input Privacy of PLONK Proving Systems via Rowhammer
Research Manuscript Architectures for Sparse, Adaptive, and Scalable Acceleration
Research Manuscript LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout
Engineering Poster ARTEMIS: Agentic AI for EDA
Engineering Poster Maximize RoI Through Glitch Power Optimization at Early Design Stage
DAC Pavilion Panel What Are VCs Looking for at DAC?
Research Manuscript From Analog to 3D Packaging: Enabling Routing and Clocking for Next-Generation Systems
Research Manuscript RM Poster Session Six
Research Manuscript Ciphershield: Safeguarding DNN Inputs from Ciphertext Side-Channels in TEE
Research Manuscript WINNER: A Wireless In-Vivo/ex-Vivo Runtime Analyzer for Intermittent Computing
Research Manuscript Placing the Future Beyond Cells: From Transistors to 3D Integration
Research Manuscript RM Poster Session Nine
Engineering Poster Gladiator Agile Silicon: A Gitops-Based PD Orchestration Framework Enabling <10-Person PD Team to Deliver CPO Tapeouts
Research Manuscript Edgesc: Universal Stochastic Computing Architecture for Efficient Edge Detection
Research Manuscript Slcross: Cross-Component System-Level Cache Side-Channel Attacks on Apple M2 SoC
Work in Progress Lockroute: A Spatial Locking Framework for Parallel Global Routing
Research Manuscript Scalable Reliability Assessment of DNNs Through Simultaneous Fault Injection
Research Manuscript Interconnect-Driven System Architecture Innovation
Research Special Session Orbitbrain: Secure and Reliable Chiplet Architecture for Space Edge AI and Orbital Data Centers
Research Manuscript RM Poster Session Five
Engineering Presentation Life at the Edge: No Faults and Perfect Timing
Engineering Poster Early DEF-Based Hierarchical Power Grid Shorts Analysis
Engineering Poster Automatic SDC Creation for Static Timing Analysis
DAC Pavilion Panel From RTL to Reality: Building Security into the Silicon Lifecycle
Research Manuscript ATOM-3D: Analytical Three-Dimensional Orientation-Aware Mixed-Size Placer
Research Manuscript DRΛMA: Detailed Routing by a Versatile Maze Routing Algorithm
Research Manuscript Expcheck: Dynamic Expert-Aware Checkpointing for Mixture-of-Experts Based Models
Research Manuscript WSC-Cost: An Accurate Cost Modeling Framework for Wafer-Scale Chips
Research Manuscript ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
Research Manuscript Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
Research Manuscript Jsplace: A Shape-Controllable and Length-Matching Placement for Rapid Single-Flux-Quantum Circuits
Research Manuscript Mappingevolve: LLM-Driven Code Evolution for Technology Mapping
Research Manuscript RM Poster Session Six
Research Manuscript L2L: Logic to Layout Exploration of Standard Cell Library Design
Engineering Presentation Hardening Security of HW IPs by Verifying Their Negative Space Formally
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Engineering Poster A Scalable Timing Analysis and Closure Methodology for Ultra-Large Designs
Engineering Presentation Lint-Free: A Generative AI Approach to Large Scale Autonomous RTL-Lint Correction
Engineering Presentation Lint-Free: A Generative AI Approach to Large Scale Autonomous RTL-Lint Correction
Engineering Presentation An Adjustable Length Compression Method for MBIST Repair Information
Research Manuscript Flowplace: Flow Matching for Chip Placement
Research Manuscript How Can Reinforcement Learning Achieve Expert-Level Placement?
China
Research Manuscript Pillarsparse: Rethinking Unstructured Sparse Formats for Tensor Cores
Research Manuscript Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
Research Manuscript Parallelizing Complementary Approximate Reachability
China
Late Breaking Results Late Breaking Results: HUSH: Silencing Inter-Core Interference in Real-Time Cache Analysis
Research Manuscript Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
Research Manuscript Notsotiny: A Large, Living Benchmark for RTL Code Generation
Work in Progress Compact ML-Based Glitch Propagation Modeling of Standard Cells
Engineering Poster AI-Enabled Flow for Silicon Area Reduction and Design Closure
Engineering Poster Design-for-FV Approach on a RISC-V Memory Page Walker
Engineering Presentation Efficient IR-Aware Powergrid Optimization
Engineering Poster Gladiator A Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance Nodes
Engineering Presentation Automated Validation of Liberty Models
Engineering Poster Identifying Weakest Links: A Cell Scoring Metric for Robust Design in Advanced Nodes
Engineering Poster Liberty-Based Profiling for IP Benchmarking
Research Manuscript ARC-SRAM: A Memory Subarray with Local Addressing and Reduced Access Energy
Engineering Presentation Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
Engineering Presentation Using ML-Assisted Side-Channel Analysis in Simulation: A Case Study on AES-GCM
Work in Progress SPICEMixer - Netlist-Level Circuit Evolution
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Research Manuscript CPW-SMO: Generating Mask Sets and Common Source for Maximum Common Process Window
Research Manuscript Compilation Tells Energy: Rethinking Power Modeling for DNN Accelerator Agile Design
Research Manuscript Memory That Thinks: Scalable, Reliable, and Secure Compute-in-Memory Systems
Research Manuscript RM Poster Session One
Research Manuscript RM Poster Session One
Research Manuscript RM Poster Session Seven
Research Manuscript Stateful Embedded Fuzzing Using Peripheral-Accurate Systemc Virtual Prototypes
Research Manuscript Notsotiny: A Large, Living Benchmark for RTL Code Generation
Research Special Session Progress and Roadmap Toward an Automated EDA R&D Engineer
Engineering Poster CDG-DNN: Scalable Test Template Generation Using Adaptive Neural Architecture for Industry Class CDG Hardware Verification
Engineering Poster SELECT: Sensitivity Based Exploration and Localisation of Event-Wise Correlated Tokens for Test Generation
Engineering Presentation STEER: Simulation of Templates Engine for Efficient Resource Usage
Engineering Presentation Efficient IR-Aware Powergrid Optimization
Research Special Session LLM- and RL-Boosted Agentic AI: the Perfect Blend for Analog/rf Circuits from Spec to Layout
Engineering Poster Vmin Reliability Through Critical Path-Aware PDN Analysis
Research Manuscript Making Sense of Job Preemption for Distributed Deep Learning Acceleration
Research Manuscript RM Poster Session Three
Research Special Session The Test Frontier: Advanced Packaging Solutions
Exhibitor Forum Closing the Loop Between AI and the Hardware That Fuels It
DAC Pavilion Panel What Are VCs Looking for at DAC?
Research Manuscript CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
Research Manuscript Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge
Research Manuscript CHiRM-DSE: CodeLLM-Based Hierarchical and Rule-Mining Guided DSE for FPGA Accelerators
Research Manuscript Crystal-KV: Efficient KV Cache Management for Chain-of-Thought LLMs via Answer-First Principle
Research Manuscript Efficient HLS Accelerator Floorplan on Multi-Die FPGA Aided by Graph Neural Networks
Research Manuscript Idealsim: Efficient Ideal Scenario Modeling for Processor Upper-Bound Performance Analysis
Late Breaking Results Late Breaking Results: Efficient MoE-ViT Gating on Edge Accelerator via Dynamic Expert Routing and Quantized Router
Research Manuscript Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
Research Manuscript SpArC: Sparse Tensor Accelerator Compilation with Scheduling and Mapping
Research Manuscript Optimizing Dynamic-Shape Neural Networks: A Unified Approach to Adaptive Tuning
Engineering Poster Xchip: A Guardrailed Agentic Gen-AI Front-End Flow from Intent to GDSII
Engineering Presentation Designing Power- and Area-Efficient Custom NPUs for Edge AI
Engineering Presentation From Concept to Confidence: The AI Evolution in Design & Verification
Engineering Presentation Automated Validation of Liberty Models
Engineering Poster Gladiator Sigma Profiling: Profiling Solution for Power Integrity Signoff
Engineering Presentation Multi-Agent Generative AI Pipeline for Assisting in Design Verification
Engineering Presentation System & Software Deployment
Engineering Presentation Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
Engineering Presentation Using ML-Assisted Side-Channel Analysis in Simulation: A Case Study on AES-GCM
Engineering Special Session Gaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect?
Engineering Poster Beyond Scripting: API Based HDL Generation
Engineering Special Session The Next Decade of Semiconductors And Transformation Through Industry, Academia, and Government
Engineering Special Session The Next Decade of Semiconductors And Transformation Through Industry, Academia, and Government
Research Manuscript Shortcircuit: Alphazero-Driven Generative Circuit Design
Late Breaking Results Automated Design of Device Fingerprinting Circuits for FPGAs
Research Manuscript Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge
Research Manuscript Beyond GPUs: Next-Generation Architectures for Modern AI Workloads
Research Manuscript DM-MARK: Software and Hardware Co-Design of Watermarking Accelerator for Authorized Diffusion Model Usage on Edge Devices
Research Manuscript RM Poster Session One
Research Manuscript Pillarsparse: Rethinking Unstructured Sparse Formats for Tensor Cores
Research Manuscript Stone-Skimming: Attacking Big-Data Analytics Applications with Page Table Walk
Research Manuscript Brain-Like Hyper-Dimensional Graph Learning System with Hardware-Efficient Adaptive Sparsity
Research Manuscript Exquant: Global Expert Ranking–guided Mixed-Precision Quantization for Efficient MoE Inference
Research Manuscript From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
Research Manuscript Strix: Re-Thinking NPU Reliability from a System Perspective
Research Manuscript Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
Research Manuscript ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
Research Manuscript Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
Research Manuscript Circuitdiff: Bridging Netlist Knowledge with RTL Based on Graph Denoising Diffusion
Research Manuscript Insights from Verification: Training a Verilog Generation LLM Using Reinforcement Learning with Testbench Feedback
Research Manuscript On-Demand Multi-Task Sparsity for Efficient Large-Model Deployment on Edge Devices
Research Manuscript Paretopilot: Global Optimization Reasoning on HLS Design Space Exploration with LLMs
Research Manuscript Amoeba: Runtime Tensor Parallel Transformation for LLM Inference Services
Research Manuscript Accshield: Operator-Aware Robust Scheduling for Fault-Tolerant AI Accelerators
Engineering Poster Risk Analysis for Chiplets, and Security Architecture
Research Manuscript Decoding the Past: Recovering Sensitive Data from SRAM Aging Imprints
Research Manuscript Closing Integrity Faster: Physics- and Learning-Based Methods for Power, EM/IR, and Thermal
Research Manuscript RM Poster Session Three
Research Manuscript Flashfps: Efficient Farthest Point Sampling for Large-Scale Point Clouds via Pruning and Caching
Research Manuscript RM Poster Session Nine
Research Manuscript Serving Intelligence at Scale: Architectural and Runtime Innovations for Large Models
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript GEMIR: Graph-Based Joint Modeling of Electromigration and IR Drop for Power Grid
Research Manuscript TRIDENT: An End-to-End Streaming Accelerator for TriSpGEMM
Research Manuscript Runtime-ADAR: Runtime Anomaly Detection and Attack Recovery in Encrypted DNNs
Research Manuscript WFH-BFs: Dynamic Defense Against DNN Bit-Flips via a Weight Function Hierarchy
China
Research Manuscript Operator-Level Acceleration for Sparse 3D Object Detection
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Research Manuscript Epicell: Electro-Physical Co-Modeling for Standard Cell PPA Prediction
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Engineering Poster Efficient Power Management in USB4 Routers
Research Manuscript Chiplanner: Physically-Aware and Timing-Driven Design Planner for 2.5D Multi-Chiplet Systems
Research Manuscript Fast, Furious, and Fault-Tolerant: Accelerating the Generative Grind
Research Manuscript GPU-Fuzz: Finding Memory Errors in Deep Learning Frameworks
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Presentation Efficient Routing and Connectivity Repair for Large-Scale Hierarchical Metal Networks
Research Manuscript Unlocking Automated Datapath Gating via Machine Learning Power Prediction
Engineering Poster Automatic SDC Creation for Static Timing Analysis
Engineering Presentation Crosstalk Effect Prediction and Optimization for Detail Routing Using CNN Models and Reinforcement Learning Flow Framework
Engineering Presentation Structure Aware Clock Tree Synthesis Using Width-Driven CTS Cell Constraints
DAC Pavilion Panel Build vs Buy: Who Owns the Intelligence Behind Tomorrow's Chips?
Engineering Poster Channel Width Optimization for IR Drop Reduction in Advanced SoCs
Engineering Presentation Efficient IR-Aware Powergrid Optimization
Engineering Presentation Leveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.ai
Engineering Presentation UVM-MS: A Novel Approach to Mixed-Signal IP Verification
Work in Progress SPICEMixer - Netlist-Level Circuit Evolution
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Work in Progress Lockroute: A Spatial Locking Framework for Parallel Global Routing
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Research Manuscript ARC-SRAM: A Memory Subarray with Local Addressing and Reduced Access Energy
Engineering Presentation Multi-Cycle Interconnect Synthesis in Small to Large Cutting Methodology
Research Manuscript SCOUT: Thermal-Aware SRAM Allocation for Real-Time DNN Tasks on Edge TPU
Research Manuscript OpenSUN: An Open Platform for Exploring Scale-Up Network Systems
Engineering Poster Dynamic CDC Verification Using SVA for Waiver Review
Engineering Poster INTENT-AWARE RDC ANALYSIS USING MINIMALLY BOOLEAN REASONING
Engineering Poster RDC Methodology: Noise Reduction and Improving Accuracy
Research Manuscript NVLLM: A 3D NAND-Centric Architecture Enabling Edge on-Device LLM Inference
Engineering Presentation AI-Assisted EDA Tools Development
Engineering Presentation Architectural Coverage Analysis and ML-Based Automated-Test Generation
Engineering Presentation Enabling AI Agent Flows for Verification Triage & Debug
Engineering Presentation Morph-Inspect: Structural Assurance for Inserted Logic
Engineering Presentation STEER: Simulation of Templates Engine for Efficient Resource Usage
Engineering Presentation Hardening Security of HW IPs by Verifying Their Negative Space Formally
Engineering Poster The Pursuit of Golden Specification: Leveraging Architecture Formal
DAC Pavilion Panel From RTL to Reality: Building Security into the Silicon Lifecycle
Research Manuscript Pioneering the Foundations of Quantum Circuit Synthesis, Compilation and Algorithmic Optimization
Research Manuscript RM Poster Session Eight
Engineering Poster Gladiator Multi Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN Model
Research Manuscript Targeted Bit-Flip Attacks on LLM-Based Agents
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Research Manuscript Pipegs: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning
Research Manuscript SpRDA: An Efficient Sparse Accelerator for Robotics Diffusion Model
Research Manuscript Ctxmem: OS-Hardware Co-Designed Tiered Memory with DRAM-SSD Hybrid CXL Devices
Research Manuscript TDH-GNN: An Efficient Topology-Driven Accelerator for Dynamic Heterogeneous GNN
Research Manuscript Crosstalk Timing Prediction via Graph Prompt Learning in Aggressor-Victim RC Networks
Research Manuscript Path-Based Timing Analysis Acceleration via Segment-Level Timing Arc Reuse
Research Manuscript Fast Template Matching for Quantum Circuits Using Hypergraph
Research Manuscript DRCA: Reliable Bitwise Logic in DRAM via Dual-Rail Compute and Access
China
Research Manuscript Pioneering the Foundations of Quantum Circuit Synthesis, Compilation and Algorithmic Optimization
Research Manuscript RM Poster Session Eight
Engineering Presentation Deep Reinforcement Learning Paradigm for Analog Design Automation
Research Manuscript Hot Chips & Cool Models: AI Turns Up the Heat on Silicon Design
Research Manuscript RM Poster Session One
Engineering Presentation Serving Hot 3D-IC on Clean and Cool Plates
Engineering Poster Gladiator 3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration
Engineering Presentation A Good Grid Can Never be IR-Responsible
Engineering Poster Hierarchical IP Block Resizing on the Fly
Engineering Special Session The Next Decade of Semiconductors And Transformation Through Industry, Academia, and Government
Research Manuscript Exploiting Movable Logical Qubits for Lattice Surgery Compilation
Engineering Presentation Architectural Coverage Analysis and ML-Based Automated-Test Generation
Engineering Presentation Enabling AI Agent Flows for Verification Triage & Debug
Exhibitor Forum SYNOPSYS: How Silicon Startups Are Addressing the AI Memory Gap
Research Manuscript Stitch: Assertion-Guided Patching of On-Chip Protocol Implementations Using LLMs
Research Special Session Modeling and Benchmarking Early Fault-Tolerant Quantum Computers
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Engineering Presentation Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
Research Manuscript PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
Research Manuscript Schemacoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting
Research Manuscript TOPCELL: Topology Optimization of Standard Cell via LLMs
Research Special Session Toward Agentic Solutions for DRC Challenges in Digital VLSI Design
Research Manuscript Hierarchical Boundary Recovery: Overcoming Synthesis Obscurity via SAT Sweeping
Research Manuscript BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis
Research Manuscript BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs
Research Manuscript Diffsp: Differentiable Sequence Pair-Based Analog Placement
Research Manuscript Flexicts: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs
Late Breaking Results Late Breaking Results: "describing" Your Way to a Functional Microfluidic Chip
Work in Progress Late Breaking Results: High-Fidelity Simulation and Real-Time Forecasting of Fluid-Solute-Coupled Microfluidics
Research Manuscript Mappingevolve: LLM-Driven Code Evolution for Technology Mapping
Research Manuscript Mixed-Structure Double-Sided Redistribution Layer Routing for Glass Interposer-Based 5.5D ICs
Research Manuscript Moduplace: LLM-Assisted Modular PCB Placement via Preference-Optimized Constraint Graph Generation
Research Manuscript Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding
Engineering Poster Gladiator LLM-Aided Cell Clustering for Placement Optimization of DRAM Peripheral Circuits
Research Manuscript Adaptive Spiking Neural Networks for Real-Time Multi-Object Detection Tasks
Engineering Poster Low Power Optimization Through Fast and Accurate Time-Based Power Analysis
Engineering Presentation Analysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous Integration
Engineering Poster Low Power Optimization Through Fast and Accurate Time-Based Power Analysis
Research Manuscript Vten: Tensor-Centric Verification Framework for Domain-Specific Accelerators
Engineering Poster SHELL: AI-Driven UVM Framework
Research Manuscript Fast Template Matching for Quantum Circuits Using Hypergraph
Engineering Poster A Novel Design Approach for Optimized EMC and Thermal Performance in Next-Generation Automotive Applications
Engineering Poster AI-Accelerated Optimization Flow for Robust Analog and Mixed-Signal Circuit Design Against Process Variation
Engineering Poster Enhancing the Robustness of Impinj RAIN RFID Design Through the Application of AI-Powered Process Flow
Engineering Presentation Screening Analog Anomality for Security Vulnerability in Digitally Verified Crypto Cores
Research Manuscript GEMIR: Graph-Based Joint Modeling of Electromigration and IR Drop for Power Grid
Research Manuscript Integrated Timing-Driven Placement for Hybrid-Bonding-Based Face-to-Face 3D ICs
Engineering Presentation Hunting RTL Glitches Before They Burn Power: A Practical RTL Success Story
Engineering Poster Slack-Exploiting Load Splitting for IR-Drop Mitigation
Engineering Poster Automotive Logic Test Power Management
Work in Progress SPICEMixer - Netlist-Level Circuit Evolution
Engineering Poster Slack-Exploiting Load Splitting for IR-Drop Mitigation
Research Manuscript RM Poster Session Two
Late Breaking Results Late Breaking Results: 3D Analytical Placement with Smoothed Multi-Die Wirelength Model
Research Manuscript TRIDENT: An End-to-End Streaming Accelerator for TriSpGEMM
Research Manuscript Legend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
Research Manuscript Path-Based Timing Analysis Acceleration via Segment-Level Timing Arc Reuse
Research Manuscript AMBER: A Unified Accelerator for Multi-Precision LLM Inference Exploiting Bit-Level Redundancy and Reconfigurability
Research Manuscript Hiband: A Hierarchical Bandwidth-Aware HB-DRAM Accelerator with Array-Level Co-Execution and Reconfigurable NoC for LLM Inference
Research Manuscript Pipegs: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning
Research Manuscript Stone-Skimming: Attacking Big-Data Analytics Applications with Page Table Walk
Research Manuscript WSC-Cost: An Accurate Cost Modeling Framework for Wafer-Scale Chips
Research Manuscript Cupilot: A Strategy-Coordinated Multi-Agent Framework for CUDA Kernel Evolution
Research Manuscript TRIDENT: An End-to-End Streaming Accelerator for TriSpGEMM
Research Manuscript AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning
Research Manuscript Exploiting Function-Family Structure in Analog Circuit Optimization
Research Manuscript Akirarust: Re-Thinking LLM-Aided Rust Repair Using a Feedback-Guided Thinking Switch
Research Manuscript Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
Research Manuscript Circuitdiff: Bridging Netlist Knowledge with RTL Based on Graph Denoising Diffusion
Research Manuscript Insights from Verification: Training a Verilog Generation LLM Using Reinforcement Learning with Testbench Feedback
Research Manuscript UniNL: Unifying Fragmented Non-Linear Operators for Efficient Edge LLM Inference
Research Manuscript Chimera: A Unified FHE Accelerator with Enhanced Compatibility for TFHE
Research Manuscript Onyx: Efficient Transaction Processing with Real Processing-in-Memory Prototypes
Engineering Presentation Hardening Security of HW IPs by Verifying Their Negative Space Formally
Research Manuscript Greenllm: SLO-Aware Dynamic Frequency Scaling for Energy-Efficient LLM Serving
Research Manuscript Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells
Late Breaking Results Late Breaking Results: A Coarse-to-Fine PCB Placement Framework via LLM-Guided Component Grouping and Group-Aware Placement
Late Breaking Results Late Breaking Results: A Fully Differentiable Rectilinear Minimum Spanning Tree Wirelength Model for Global Placement
Late Breaking Results Late Breaking Results: LLM-Driven Constraint Generation and Deferred Shape Exploration for Analog IC Floorplanning
Late Breaking Results Late Breaking Results: Merge-Aware Placement and DP-Based Wave Propagation Routing for Scalable Flip-FET Cell Layout Synthesis
Research Special Session Qubic: An Open-Source Control System for Enabling Full-Stack Quantum Co-Design
China
Research Manuscript Exploiting Dependency and Parallelism: Real-Time Scheduling and Analysis for GPU Tasks
Research Manuscript Operator-Level Acceleration for Sparse 3D Object Detection
Research Manuscript Etherssd: An In-Storage Ethereum Analytics Platform with Minimized I/O and Authentication Overhead
Research Manuscript Freebit: Unleashing the Performance Potential of Low-Bit LLMs Through PIM
Research Manuscript PIMGRAG: A Heterogeneous PIM Architecture for Graph-Based Retrieval-Augmented Generation
Research Manuscript SpecANNS: Accelerating Graph-Based Approximate Nearest Neighbor Search with Speculative In-Storage Computing
Research Manuscript TierANNS: Scalable Graph-Based ANNS with CXL-Enabled Tiered Data Placement
Research Manuscript LRTA: Routability-Driven 3D-Aware Track Assignment with Layer Reassignment
Research Manuscript NASiC: 3D NAND-Based CAM-Selected Multibit CIM Architecture for Efficient On-Device Mixture-of-Experts LLM Inference
Research Manuscript PD-Swap: Prefill–decode Logic Swapping for End-to-End LLM Inference on Edge FPGAs via Dynamic Partial Reconfiguration
Research Manuscript RM Poster Session Seven
Late Breaking Results Late Breaking Results: QUBO Approaches to Logic Equivalence Checking and Testing
Research Manuscript Enabling AI ASICs for Zero Knowledge Proof
Research Manuscript A Differentiable Approach to Task Graph Partitioning: A Case Study in RTL Simulation
Research Manuscript SP2RINT: Spatially-Decoupled Physics-Constrained Progressive Inverse Optimization for Diffractive Optical Neural Network Training
Research Manuscript Self-Driving EDA: Agents, Benchmarks, and Evolving Toolchains
Research Manuscript Ihyperg: Incremental Hypergraph Partitioning on GPU
Research Manuscript An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference
Research Manuscript CPA-BNN: A Secure and Efficient CIM and PUF Architecture for BNN Accelerator
Research Manuscript Deinfer: Efficient Parallel Inferencing for Decomposed Large Language Models
Research Manuscript Deinfer: Efficient Parallel Inferencing for Decomposed Large Language Models
Research Manuscript Runtime-ADAR: Runtime Anomaly Detection and Attack Recovery in Encrypted DNNs
China
Engineering Special Session Quantum to Software Development
Research Special Session Satreg: Regression-Based Neural Architecture Search for Lightweight Satellite Image Segmentation
Late Breaking Results Late Breaking Results: 3D Analytical Placement with Smoothed Multi-Die Wirelength Model
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Engineering Presentation Optimizing Digital SOC Designs, One Cell at a Time Using AI Transistor-Level Sizing
Research Manuscript Raise the Shields: A Modular RISC-V Extension for Post Quantum Cryptography
Engineering Presentation A Rule-Aware Layout Conversion Framework for Back-End Physical Design
Engineering Presentation Adaptive AI and Additive AI Techniques for High-Sigma Standard Cell Verification
Research Manuscript Making Sense of Job Preemption for Distributed Deep Learning Acceleration
Engineering Poster Gladiator Flexible & Scalable Network Modeling for AI/HPC Network Verification
I
Research Manuscript ENACT: Ensemble Neural Fields for Reactive Robot Control
Research Manuscript Scaling Intelligence for the Physical World
Research Manuscript Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Research Manuscript Light-Bound Transformers: Hardware-Anchored Robustness for Silicon-Photonic Computer Vision Systems
Research Manuscript RM Poster Session Six
Research Manuscript TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI
Engineering Poster Gladiator A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs
Engineering Poster Hierarchical Cost-Efficient IR Methodology for AI SoCs
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Engineering Presentation Staged Snapshots for Firmware-Hardware Collaborative Debug
Engineering Poster Gladiator Cost-Based Partial Subgraph Matching for Circuit Pattern Recognition
Engineering Presentation Graph Isomorphism for Explainable Transistor-Level Circuit Comparison
Engineering Poster Gladiator A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs
Engineering Poster Silicon Correlation of Voltage Droop Mitigation Scheme
Engineering Poster Fair Play in the Multiplex: Formal Verification of Complex Arbmux Designs
Engineering Presentation No Credit Where Credit Is Due: Quiesced Formal Check for PCIe Crediting
Engineering Poster Gladiator Outsmarting State Space Complexity Through Proven Reset Abstraction Stratergies
Engineering Presentation Weeding Out Timing Gaps and Improving Performance of DDR Controllers Using Formal Verification
Engineering Poster Vmin Reliability Through Critical Path-Aware PDN Analysis
Engineering Presentation A Programmable, Synthesizable CMOS Analog Optimization IP Core for Real-Time Control
Engineering Poster Multi-Cycle Dynamic Vectorless Analysis for Improved PDN Signoff
Engineering Presentation Past Present and Future of CDC & RDC Glitches: Improved Glitch Checker (IGC)
Engineering Presentation Lint-Free: A Generative AI Approach to Large Scale Autonomous RTL-Lint Correction
Engineering Presentation Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper Generation
Engineering Presentation Accelerating X-State Aware Power Simulation Using Advanced Hardware Emulation
Engineering Presentation Shifting System-Level Verification Left with Firmware-Driven Execution
Engineering Presentation Enabling PSS-Driven Early SoC Verification By Enriching IP-XACT Information
Engineering Poster Channel Width Optimization for IR Drop Reduction in Advanced SoCs
Engineering Poster ML Based Design Space Prediction for Power Grid Optimization
Engineering Presentation A Unified QA Framework for Intel Library Validation Using Siemens Solido Crosscheck
Engineering Poster Multi-Cycle Dynamic Vectorless Analysis for Improved PDN Signoff
Research Manuscript Attestllm: Efficient Attestation Framework for Billion-Scale On-Device LLMs
DAC Pavilion Panel Is EDA AI Delivering on Its ROI Promise?
Engineering Presentation A Probe-Based Time-Domain Methodology for Dynamic Thermal Management in Stacked-Die Architectures
Research Manuscript Pioneering AI and GPU-Powered Techniques for Advanced Timing Analysis and Optimization
Research Manuscript RM Poster Session One
Engineering Presentation DFT Ready Design with SCO Canvas : Shift Left of DFT Designs
Engineering Poster Library PPA DTCO with Library Profiler
Research Manuscript Flip-FET-Based VLSI Design Framework with Congestion-Aware Dual-Side Routing
Engineering Poster Revisiting PDN at the MOL Boundary: A Placement-Aware Power Delivery Flow
Engineering Presentation Local Layout Effect Coverage Check Using Artificial Neural Network-Based Surrogate Models
Engineering Poster TAWT: Towards Autonomous Wrapper Tuning
Engineering Poster Early DEF-Based Hierarchical Power Grid Shorts Analysis
Engineering Presentation Hunting RTL Glitches Before They Burn Power: A Practical RTL Success Story
Research Manuscript Integrated Timing-Driven Placement for Hybrid-Bonding-Based Face-to-Face 3D ICs
Research Manuscript GEMIR: Graph-Based Joint Modeling of Electromigration and IR Drop for Power Grid
Research Manuscript Pipegs: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning
Research Manuscript SpRDA: An Efficient Sparse Accelerator for Robotics Diffusion Model
Research Manuscript WSC-Cost: An Accurate Cost Modeling Framework for Wafer-Scale Chips
Research Manuscript Advancing the Frontier of Neuromorphic Learning Systems
Research Manuscript RM Poster Session Two
Late Breaking Results Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond
Research Manuscript ALOHA: Area-Efficient and Low-Power Stochastic Computing with Hammersley Sequences
Research Manuscript Adana: Accelerating Large Language Models via Adaptive Nonuniform Asymmetric Quantization
China
Research Manuscript Bident: Optical Logic Synthesis via Optimal Configuration of Binary-Combiner Trees
Late Breaking Results Late Breaking Results: Power Mesh Construction for 3D-IC with Backside Power Delivery
Research Manuscript Enabling AI ASICs for Zero Knowledge Proof
Research Manuscript SSD Reforge: Dynamic Parity Management to Extend SSD Lifetime Under Aging
Research Manuscript Akirarust: Re-Thinking LLM-Aided Rust Repair Using a Feedback-Guided Thinking Switch
Research Manuscript Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
Research Manuscript Per Flow Asynchronous Traffic Shaping in Time Sensitive Networking
Research Manuscript Akirarust: Re-Thinking LLM-Aided Rust Repair Using a Feedback-Guided Thinking Switch
Research Manuscript Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
Research Manuscript Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
Research Manuscript Circuitdiff: Bridging Netlist Knowledge with RTL Based on Graph Denoising Diffusion
Research Manuscript From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
Research Manuscript Insights from Verification: Training a Verilog Generation LLM Using Reinforcement Learning with Testbench Feedback
Research Manuscript Paretopilot: Global Optimization Reasoning on HLS Design Space Exploration with LLMs
Research Manuscript Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging
Research Manuscript Strix: Re-Thinking NPU Reliability from a System Perspective
Research Manuscript DCTS: Differentiable Clock Tree Synthesis Based on Probabilistic Graphical Model
Research Manuscript Beyond Exact: Tight WCET Analysis of GPU Kernels with Branch Divergence
Engineering Poster Gladiator 3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration
Research Manuscript A Locality-Aware Temporal Motif Mining Accelerator with Chunk-Based Search Tree Expansion
Research Manuscript An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference
Research Manuscript Dart: Towards Redundancy-Free RTL Simulation via DAG-Driven Execution
Research Manuscript Dypamear: Efficient and Scalable Dynamic Graph Pattern Mining on Practical Processing-in-Memory Architecture
Research Manuscript Fusedot: A Multiplication-Fused Dot Product Accelerator for Efficient LLM Inference
Research Manuscript Hbspec: A Hybrid-Bonding-Based Heterogeneous Accelerator for Efficient Tree-Structured Speculative Decoding
Research Manuscript BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis
Research Manuscript BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs
Research Manuscript DiffDEG: Diffusion-Enhanced Design Evolution Graph Representation Learning for Post-Layout Optimization
Research Manuscript Flexicts: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs
Research Manuscript Stone-Skimming: Attacking Big-Data Analytics Applications with Page Table Walk
Engineering Poster Unifying Pre- and Post-Silicon Software Validation Through Modeling
Research Manuscript Advances in 3D/2.5D Physical Design
Engineering Presentation Advanced Hard IP Integration Requirement Extraction and Checker
Engineering Poster CDG-DNN: Scalable Test Template Generation Using Adaptive Neural Architecture for Industry Class CDG Hardware Verification
Engineering Poster SELECT: Sensitivity Based Exploration and Localisation of Event-Wise Correlated Tokens for Test Generation
Engineering Presentation STEER: Simulation of Templates Engine for Efficient Resource Usage
Engineering Presentation Staged Snapshots for Firmware-Hardware Collaborative Debug
Engineering Presentation Enabling AI Agent Flows for Verification Triage & Debug
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
China
Engineering Presentation A Rule-Aware Layout Conversion Framework for Back-End Physical Design
K
Engineering Poster Advanced Hard IP Integration Requirement Extraction and Checker
Engineering Poster TAWT: Towards Autonomous Wrapper Tuning
Engineering Presentation Deep Reinforcement Learning Paradigm for Analog Design Automation
Research Manuscript HW-Router: Hardware-Aware Routing for Scalable Multi-LLM Serving
Research Special Session The Emerging Revolution in Spatial AI is Distinct from the LLM Revolution
Research Manuscript RM Poster Session Four
Research Manuscript Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
Additional Meeting Open-Source EDA Birds-of-a-Feather Session
Research Special Session Progress and Roadmap Toward an Automated EDA R&D Engineer
Engineering Presentation Correct-by-Construction Framework for Robustness Against Divergent Voltage Drops and High Clock Divergence
Engineering Poster Differential Validator: Ensuring SoC ROM to Hierarchical Blocks Node Voltage Integrity
Engineering Presentation Optimizing Reliability EM Sign-Off for 2nm Mobile SoCs
Engineering Presentation Design Spec to Die-Size Estimation Using ML Based Framework for Automotive SoCs
Research Manuscript RM Poster Session Four
Engineering Poster Gladiator A Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance Nodes
Engineering Presentation Automated Validation of Liberty Models
Engineering Poster Identifying Weakest Links: A Cell Scoring Metric for Robust Design in Advanced Nodes
Engineering Poster Liberty-Based Profiling for IP Benchmarking
Engineering Presentation Architectural Formal Verification of Configurable Address Translation Logic for Early Bug Exposers
Engineering Poster Gladiator Multi Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN Model
Engineering Poster A Scalable Timing Analysis and Closure Methodology for Ultra-Large Designs
Research Manuscript Scalable and Adaptive Parallel Training of Graph Transformer on Large Graphs
Engineering Presentation Past Present and Future of CDC & RDC Glitches: Improved Glitch Checker (IGC)
Research Manuscript L2L: Logic to Layout Exploration of Standard Cell Library Design
Research Manuscript Adaptive Spiking Neural Networks for Real-Time Multi-Object Detection Tasks
Research Manuscript Adaptive Spiking Neural Networks for Real-Time Multi-Object Detection Tasks
Engineering Poster Routability Optimizing Methodology Using Flexible Pin
Engineering Poster Real-Time Local Layout Effects Analysis for Advanced Design Optimization
Engineering Presentation A Rule-Aware Layout Conversion Framework for Back-End Physical Design
Engineering Presentation Local Layout Effect Coverage Check Using Artificial Neural Network-Based Surrogate Models
Research Manuscript Making Sense of Job Preemption for Distributed Deep Learning Acceleration
Research Manuscript Differentiable Fill Insertion with Explicit Delay Optimization
Research Manuscript GTX: Graph Transformer for Parasitic Extraction on Analog Circuits
Engineering Presentation Accelerating X-State Aware Power Simulation Using Advanced Hardware Emulation
Engineering Presentation Shifting System-Level Verification Left with Firmware-Driven Execution
Engineering Poster Reduced Order Modelling (ROM) Based Full Chip EMIR Signoff
Engineering Poster Silicon Correlation of Voltage Droop Mitigation Scheme
Engineering Presentation Hardening Security of HW IPs by Verifying Their Negative Space Formally
Engineering Poster Automotive Logic Test Power Management
Engineering Presentation Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
Engineering Presentation Using ML-Assisted Side-Channel Analysis in Simulation: A Case Study on AES-GCM
Research Manuscript Robust and Trusted AI Systems: Attacks, Defenses, and Hardware Reliability
Exhibitor Forum AI-Native Workflows from Architecture to Production Readiness
United Arab Emirates
Engineering Presentation Optimizing Reliability EM Sign-Off for 2nm Mobile SoCs
Engineering Presentation An Adjustable Length Compression Method for MBIST Repair Information
Research Manuscript Notsotiny: A Large, Living Benchmark for RTL Code Generation
Research Manuscript Galaxydit: Efficient Video Generation with Guidance Alignment and Adaptive Proxy in Diffusion Transformers
Research Special Session Toward Agentic Solutions for DRC Challenges in Digital VLSI Design
Engineering Presentation Comprehensive Physical Verification Approach for Heterogeneous 2.5/3D Integration
Research Manuscript TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI
Work in Progress A Fast and Accurate Surrogate Model for Clock-Mesh Timing Analysis
Engineering Poster Reduced Order Modelling (ROM) Based Full Chip EMIR Signoff
Engineering Presentation Crosstalk Effect Prediction and Optimization for Detail Routing Using CNN Models and Reinforcement Learning Flow Framework
Engineering Presentation Structure Aware Clock Tree Synthesis Using Width-Driven CTS Cell Constraints
Engineering Presentation A Programmable, Synthesizable CMOS Analog Optimization IP Core for Real-Time Control
Engineering Special Session Analog Intelligence: Physics-Aware AI for Faster, More Accurate Verification
Research Manuscript Design for the Unpredictable: Resilience and Adaptation in AIoT
Research Manuscript RM Poster Session Four
Engineering Presentation Adaptive AI and Additive AI Techniques for High-Sigma Standard Cell Verification
Engineering Poster Library PPA DTCO with Library Profiler
Research Manuscript MXP: A Posit-Inspired Microscaling Format for Vision-Language Tasks
Research Manuscript Generative AI and Graph-Based Learning for Next-Gen Circuit & Device Simulation
Research Manuscript Design for the Unpredictable: Resilience and Adaptation in AIoT
Research Manuscript RM Poster Session Four
Research Special Session Near-Memory Processing is Becoming a Reality
Research Manuscript ARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing
Engineering Poster Low Power Optimization Through Fast and Accurate Time-Based Power Analysis
Engineering Poster Revisiting PDN at the MOL Boundary: A Placement-Aware Power Delivery Flow
Engineering Poster Routability Optimizing Methodology Using Flexible Pin
Research Manuscript MXP: A Posit-Inspired Microscaling Format for Vision-Language Tasks
Engineering Presentation A Rule-Aware Layout Conversion Framework for Back-End Physical Design
Engineering Presentation Analysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous Integration
Research Manuscript Test Point Insertion with ATPG-Free Self-Supervised Learning
Research Manuscript CoX-MoE: Coalesced Expert Execution for High-Throughput MoE Inference with AMX-Enabled CPU-GPU Co-Execution
Research Manuscript MASQ: Accelerating Masked Diffusion via Stage-Wise Multi-Precision Quantization
Research Manuscript Keeping PIM Busy: Eliminating Execution Overheads for Full Throughput
Research Manuscript ARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing
Engineering Presentation Adaptive QoS Optimization for SoC Performance Enhancement Using Dueling Double Deep Q-Networks
Research Manuscript Efficient LLM and MoE Inference on Specialized Hardware
Research Manuscript RM Poster Session Four
Research Manuscript MASQ: Accelerating Masked Diffusion via Stage-Wise Multi-Precision Quantization
Research Manuscript PRISM: Priority Aware Shared Scale Microscaling Format for 4-Bit Quantization
Research Manuscript Tdsnap: Enabling Secure Function-as-a-Service with Trusted Domain Snapshots
Research Manuscript ARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing
Research Manuscript TopGQ: Fast GNN Post-Training Quantization Leveraging Topology Information
Research Manuscript Intelligence-Aware Software: Efficiency, Reliability, and Security in the LLM Era
Research Manuscript RM Poster Session Seven
Engineering Presentation Enabling PSS-Driven Early SoC Verification By Enriching IP-XACT Information
Late Breaking Results Late Breaking Results: Fisher-Guided Selective Error Reconstruction for Quantized LLMs
Research Manuscript CO-MAC: A Center-Out Ordered Stochastic MAC for Low-Latency Inference
Engineering Poster Accelerating DFT Verification and Enhancing Debuggability Using Veloce-Based Full Chip Gate-Level Emulation
Engineering Presentation Accelerating X-State Aware Power Simulation Using Advanced Hardware Emulation
Engineering Presentation Adaptive QoS Optimization for SoC Performance Enhancement Using Dueling Double Deep Q-Networks
Engineering Presentation Building an Ontology-Driven Knowledge Graph for Constraint-Aware Navigation of Semiconductor Design Documents
Engineering Presentation Enabling Automated Software Testing in Emulation Environments via Fastboot Virtualization and On-Premises LLM-Based Failure Analysis
Engineering Presentation Enabling PSS-Driven Early SoC Verification By Enriching IP-XACT Information
Engineering Poster Pre-Silicon Real Workloads Validation: Integration of Wireless Network Testers and Hardware Emulation via Virtualization
Engineering Presentation Shifting System-Level Verification Left with Firmware-Driven Execution
Engineering Poster Unifying Pre- and Post-Silicon Software Validation Through Modeling
DAC Pavilion Panel Agentic AI in EDA: Who's in Control?
Engineering Presentation Enabling AI Agent Flows for Verification Triage & Debug
Research Manuscript EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation
Research Special Session Co-Designed Compute Memories for Ultra-Efficient DNN Inference
Research Manuscript Chimera: A Unified FHE Accelerator with Enhanced Compatibility for TFHE
Research Manuscript GTX: Graph Transformer for Parasitic Extraction on Analog Circuits
Engineering Presentation Past Present and Future of CDC & RDC Glitches: Improved Glitch Checker (IGC)
Engineering Presentation Custom Implementation of High-Speed Digital Blocks Using Virtuoso Studio
Research Special Session Entertainment AI and Distributed Fan Experience
DAC Pavilion Panel Agentic AI in EDA: Who's in Control?
Research Manuscript Efficient & Edge-Ready AI Systems
Research Manuscript RM Poster Session Five
Engineering Poster Gladiator A Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance Nodes
Research Manuscript Expcheck: Dynamic Expert-Aware Checkpointing for Mixture-of-Experts Based Models
Research Manuscript Attestllm: Efficient Attestation Framework for Billion-Scale On-Device LLMs
Research Manuscript Enabling AI ASICs for Zero Knowledge Proof
Work in Progress Lockroute: A Spatial Locking Framework for Parallel Global Routing
Research Manuscript Scalable Reliability Assessment of DNNs Through Simultaneous Fault Injection
Engineering Presentation Optimizing Reliability EM Sign-Off for 2nm Mobile SoCs
Research Manuscript Exploiting Movable Logical Qubits for Lattice Surgery Compilation
Engineering Presentation Screening Analog Anomality for Security Vulnerability in Digitally Verified Crypto Cores
Research Manuscript RM Poster Session Five
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Engineering Poster Silicon Correlation of Voltage Droop Mitigation Scheme
Engineering Poster Identifying Weakest Links: A Cell Scoring Metric for Robust Design in Advanced Nodes
Engineering Poster Liberty-Based Profiling for IP Benchmarking
Late Breaking Results Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond
Engineering Presentation Leveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.ai
Engineering Poster Maximize RoI Through Glitch Power Optimization at Early Design Stage
Engineering Poster ML Based Design Space Prediction for Power Grid Optimization
Engineering Poster New Thermal Analysis Workflow for 3DIC Designs
Engineering Presentation Weeding Out Timing Gaps and Improving Performance of DDR Controllers Using Formal Verification
Engineering Poster Mixed Transistor Design Closure
Engineering Presentation Lint-Free: A Generative AI Approach to Large Scale Autonomous RTL-Lint Correction
Engineering Poster Multi-Agent Automated Formal Verification for Automative Applications
Engineering Presentation Progress-Based Timeout Debug for Scalable SoC Verification
Engineering Presentation Intelligent Clock Domain Crossing: Activity-Aware Synchronization for Low-Power SoCs
Research Manuscript Enabling AI ASICs for Zero Knowledge Proof
Engineering Special Session The Heterogeneous Future of Agentic AGI: Challenges and Opportunities!
Engineering Poster Dynamic CDC Verification Using SVA for Waiver Review
Engineering Poster INTENT-AWARE RDC ANALYSIS USING MINIMALLY BOOLEAN REASONING
Engineering Poster RDC Methodology: Noise Reduction and Improving Accuracy
Engineering Poster Slack-Exploiting Load Splitting for IR-Drop Mitigation
Engineering Presentation AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Engineering Presentation AI-Enabled EDA Cloud Infrastructure and Design Optimization for Next-Generation Semiconductor Design
Engineering Poster Library PPA DTCO with Library Profiler
Work in Progress Accelerating Functional Fault Grading for Flash and DRAM Designs
Research Manuscript ARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing
Research Manuscript ARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing
L
Late Breaking Results Late Breaking Results: Power Mesh Construction for 3D-IC with Backside Power Delivery
Engineering Poster Gladiator 3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration
Research Manuscript iPCL-M: Pre-Training of Chip Layout for Metrics Evaluation and Optimization
Engineering Poster Hierarchical IP Block Resizing on the Fly
Engineering Poster Reduced Order Modelling (ROM) Based Full Chip EMIR Signoff
Engineering Presentation No Credit Where Credit Is Due: Quiesced Formal Check for PCIe Crediting
Engineering Poster New Thermal Analysis Workflow for 3DIC Designs
Engineering Presentation Automated Verification and Performance Analysis for Chiplets
Engineering Poster Automatic SDC Creation for Static Timing Analysis
Research Special Session Advanced Packaging: From Concept to Deployment
China
Research Manuscript PMU-Faker: The Apparently Harmless Performance Monitoring Unit Events Are Actually Harmful
Research Manuscript Unveiling the Security Risks Driven by the Hardware Interrupts
Research Manuscript Enabling AI ASICs for Zero Knowledge Proof
Research Manuscript Shared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen Synthesis
Research Manuscript Unlocking Automated Datapath Gating via Machine Learning Power Prediction
Engineering Poster Resistive Model-Based via Optimizatiion
Engineering Poster Agentic Time-Travel Debugging for HLS Code
Research Manuscript PRISM: Priority Aware Shared Scale Microscaling Format for 4-Bit Quantization
Engineering Presentation A Mixed-Domain Modeling Approach for Hatched Ground Planes in 3D Chiplet Die-to-Die Interconnect
Research Manuscript REACT: Rapid Error-Tolerant Activation Compressor for Efficient Transformer Training
Research Manuscript Vten: Tensor-Centric Verification Framework for Domain-Specific Accelerators
Research Manuscript MASQ: Accelerating Masked Diffusion via Stage-Wise Multi-Precision Quantization
Engineering Poster SHELL: AI-Driven UVM Framework
Research Manuscript Differentiable Fill Insertion with Explicit Delay Optimization
Research Manuscript Differentiable Fill Insertion with Explicit Delay Optimization
Research Manuscript MXP: A Posit-Inspired Microscaling Format for Vision-Language Tasks
Research Manuscript Test Point Insertion with ATPG-Free Self-Supervised Learning
Research Manuscript Adaptive Spiking Neural Networks for Real-Time Multi-Object Detection Tasks
Engineering Poster Gladiator LLM-Aided Cell Clustering for Placement Optimization of DRAM Peripheral Circuits
Research Manuscript RM Poster Session Three
Research Manuscript Winning the Token-Time Wars: Low-Bit LLMs, Faster MoE, and KV-Cache Systems
Engineering Poster Low Power Optimization Through Fast and Accurate Time-Based Power Analysis
Research Manuscript MXP: A Posit-Inspired Microscaling Format for Vision-Language Tasks
Engineering Presentation Enabling PSS-Driven Early SoC Verification By Enriching IP-XACT Information
Research Manuscript Vten: Tensor-Centric Verification Framework for Domain-Specific Accelerators
Research Manuscript SCOUT: Thermal-Aware SRAM Allocation for Real-Time DNN Tasks on Edge TPU
Research Manuscript Accelerators and Design Methods for AI Workloads
Research Manuscript RM Poster Session Seven
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
Research Manuscript SCOUT: Thermal-Aware SRAM Allocation for Real-Time DNN Tasks on Edge TPU
Work in Progress Accelerating Functional Fault Grading for Flash and DRAM Designs
Research Manuscript TopGQ: Fast GNN Post-Training Quantization Leveraging Topology Information
Research Manuscript ARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing
Engineering Presentation Adaptive AI and Additive AI Techniques for High-Sigma Standard Cell Verification
Engineering Poster Real-Time Local Layout Effects Analysis for Advanced Design Optimization
Research Manuscript A Differentiable Approach to Task Graph Partitioning: A Case Study in RTL Simulation
Research Manuscript Ihyperg: Incremental Hypergraph Partitioning on GPU
Engineering Poster Real-Time Local Layout Effects Analysis for Advanced Design Optimization
Engineering Presentation Enabling PSS-Driven Early SoC Verification By Enriching IP-XACT Information
Engineering Presentation Analysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous Integration
Research Manuscript ARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing
Work in Progress Accelerating Functional Fault Grading for Flash and DRAM Designs
Engineering Presentation Enabling PSS-Driven Early SoC Verification By Enriching IP-XACT Information
Engineering Presentation Analysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous Integration
China
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript CARAMEL: Boosting Device Utilization in Control Flow Auditing
Research Manuscript Stateful Embedded Fuzzing Using Peripheral-Accurate Systemc Virtual Prototypes
Additional Meeting Open-Source EDA Birds-of-a-Feather Session
Engineering Presentation Shifting System-Level Verification Left with Firmware-Driven Execution
Research Manuscript TOPCELL: Topology Optimization of Standard Cell via LLMs
Research Manuscript Cupilot: A Strategy-Coordinated Multi-Agent Framework for CUDA Kernel Evolution
Research Manuscript Knowledge-Driven Hybrid SSD Management Enhanced by Fine-Tuned LLMs
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript RM Poster Session Seven
Research Manuscript Rethinking AI Compute: Cross-Layer Co-Design Beyond Conventional GPUs
Engineering Poster Multi-Cycle Dynamic Vectorless Analysis for Improved PDN Signoff
Research Manuscript PLONK-Hammer:breaking Input Privacy of PLONK Proving Systems via Rowhammer
Research Manuscript KL-MoE: A Hierarchical MoE Pruning Framework Exploiting KL Divergence
Research Manuscript Weaver: Stratified Expert Scheduling for Memory-Constrained MoE Inference
Research Manuscript Nash: A Neighbor-Aware Shared Memory Design on GPU for Accelerating AI Workloads
Research Manuscript A Hamiltonian-Guided Pre-Trainer for Variational Quantum Algorithms
Research Manuscript Algorithm and Hardware Co-Design for Efficient Complex-Valued Uncertainty Estimation
Research Manuscript Optimized Time-Dependent Hamiltonian Evolution Quantum Solver for Power System Transient Computations
Research Manuscript RM Poster Session Five
Research Manuscript ATLAS: Asynchronous Topological Learning for Accurate FIT Prediction via Decoupled Graph Neural Networks
Research Manuscript Chimera: A Unified FHE Accelerator with Enhanced Compatibility for TFHE
Research Manuscript STAC: Spatial-Temporal Activation Contextualization for Resilient LLM Inference
Research Manuscript Dataflowgen: An MLIR-Based Compiler for Efficient Dataflow Accelerator Generation
Research Manuscript Dynamic-Cost Area Recovery for Fracturable LUT-Based FPGAs
Research Manuscript Parallelizing Complementary Approximate Reachability
Research Manuscript Strix: Re-Thinking NPU Reliability from a System Perspective
Late Breaking Results Late Breaking Results: A Coarse-to-Fine PCB Placement Framework via LLM-Guided Component Grouping and Group-Aware Placement
Late Breaking Results Late Breaking Results: A Fully Differentiable Rectilinear Minimum Spanning Tree Wirelength Model for Global Placement
Research Manuscript Analytically-Derived Hybrid Net–pin Weighting for Timing-Driven Global Placement
Research Manuscript An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference
Research Manuscript RAM-CGRA: Reachability-Aware Mapping for CGRAs
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Research Manuscript Hero: Adaptive Orchestration of Retrieval-Augmented Generation on Heterogeneous Mobile SoC
Research Manuscript KERV: Kinematic-Rectified Speculative Decoding for Embodied VLA Models
Additional Meeting 2026 DAC Early Career Workshop
Research Manuscript DRIFT: Harnessing Inherent Fault Tolerance for Efficient and Reliable Diffusion Model Inference
Research Manuscript DySL-VLA: Efficient Vision-Language-Action Model Inference via Dynamic-Static Layer-Skipping for Robot Manipulation
Research Manuscript Edgesc: Universal Stochastic Computing Architecture for Efficient Edge Detection
Research Manuscript KEEP: A KV-Cache-Centric Memory Management System for Efficient Embodied Planning
Research Manuscript NASiC: 3D NAND-Based CAM-Selected Multibit CIM Architecture for Efficient On-Device Mixture-of-Experts LLM Inference
Research Manuscript Orchestrating Dual-Boundaries: An Arithmetic Intensity Inspired Acceleration Framework for Diffusion Language Models
Research Manuscript RM Poster Session Six
Research Manuscript S2CIM: A Secure-Computation and Secure-Storage Compute-in-Memory Architecture with Circuit-Algorithm Co-Design for Efficient and Trustworthy Edge Inference
Research Manuscript Structuring the Blueprint: Scalable Partitioning and Early-Stage Floorplanning
Research Manuscript Compart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning
Research Manuscript G-Power: Architecture-Level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs
Research Manuscript FBS: Accelerating CNN Inference over RNS-CKKS with Fewer Bootstrapping Sparsity
Research Manuscript An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference
Research Manuscript Fast Template Matching for Quantum Circuits Using Hypergraph
Research Manuscript Dart: Towards Redundancy-Free RTL Simulation via DAG-Driven Execution
Research Manuscript EASY-ZKP: An End-to-End FPGA-Accelerated System for Zero Knowledge Proofs
Research Manuscript EASY-ZKP: An End-to-End FPGA-Accelerated System for Zero Knowledge Proofs
Engineering Poster Automotive Logic Test Power Management
Research Manuscript Agent-Per-Qubit: Automated Qubit Placement for Fault-Tolerant Quantum Computing
Research Manuscript Agent-Per-Qubit: Automated Qubit Placement for Fault-Tolerant Quantum Computing
Research Manuscript Accshield: Operator-Aware Robust Scheduling for Fault-Tolerant AI Accelerators
Research Manuscript Nash: A Neighbor-Aware Shared Memory Design on GPU for Accelerating AI Workloads
Research Manuscript Move Less, Compute More: Memory-Centric Architectures for AI
Research Manuscript iPCL-M: Pre-Training of Chip Layout for Metrics Evaluation and Optimization
Research Manuscript Efficient HLS Accelerator Floorplan on Multi-Die FPGA Aided by Graph Neural Networks
Late Breaking Results Late Breaking Results: HUSH: Silencing Inter-Core Interference in Real-Time Cache Analysis
Research Manuscript Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Research Manuscript COLA: Enabling Low-Latency Reads for Flash-Based SSDs via Code Length Adaptation
Research Manuscript PRISM: Dynamic Primitive-Based Forecasting for Large-Scale GPU Cluster Workloads
Research Manuscript CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
Research Manuscript Amoeba: Runtime Tensor Parallel Transformation for LLM Inference Services
Research Manuscript RM Poster Session Seven
Research Manuscript From Analog to 3D Packaging: Enabling Routing and Clocking for Next-Generation Systems
Research Special Session When Generative AI Meets Analog Design: A Journey From Agent to Expert?
Research Manuscript Alphaplacer: Analog Placement Enhanced by Monte Carlo Tree Search
Research Manuscript Diffsp: Differentiable Sequence Pair-Based Analog Placement
Research Manuscript GRACE: A Ground Plane Generation and Re-Routing Aware Co-Design Engine
Research Manuscript Knowledge-Driven Hybrid SSD Management Enhanced by Fine-Tuned LLMs
Late Breaking Results Late Breaking Results: QUBO Approaches to Logic Equivalence Checking and Testing
Research Manuscript Composable Systems- The Catalyst for Memory, Acceleration, and Design Tools
Late Breaking Results Neural Subgraph Matching for Hardware Decompilation in Gate-Level Netlists
Engineering Presentation Lint-Free: A Generative AI Approach to Large Scale Autonomous RTL-Lint Correction
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Research Manuscript Marlin: I/O-Efficient Prefix KV Cache Retrieval for Long-Prefix LLM Serving
Research Manuscript Throughput-Oriented Speculative Decoding via Intra-Device Parallelism
Research Manuscript LRTA: Routability-Driven 3D-Aware Track Assignment with Layer Reassignment
Research Manuscript Accelerating AI+SAR Applications Through Enhanced Graph Optimization
Research Manuscript Per Flow Asynchronous Traffic Shaping in Time Sensitive Networking
Research Manuscript Lhgstore: An In-Memory Learned Graph Storage for Fast Updates and Analytics
China
Research Manuscript Unveiling the Security Risks Driven by the Hardware Interrupts
Research Manuscript GPU-Fuzz: Finding Memory Errors in Deep Learning Frameworks
Research Manuscript Targeted Bit-Flip Attacks on LLM-Based Agents
Engineering Poster Efficient Power Management in USB4 Routers
Research Manuscript PLONK-Hammer:breaking Input Privacy of PLONK Proving Systems via Rowhammer
Research Manuscript Hyspecpro: Scalable Hypergraph Partitioning via Spectral Projection Optimization
Research Manuscript Placing the Future Beyond Cells: From Transistors to 3D Integration
Research Manuscript RM Poster Session Nine
Research Manuscript Schemacoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting
Research Manuscript BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis
Research Manuscript BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs
Research Manuscript Flexicts: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs
Late Breaking Results Late Breaking Results: "describing" Your Way to a Functional Microfluidic Chip
Research Manuscript Coordinated Clip-Wise Gradient Scheduling for Full-Chip ILT via Policy Learning
Research Manuscript GRACE: A Ground Plane Generation and Re-Routing Aware Co-Design Engine
Research Manuscript Beyond Exact: Tight WCET Analysis of GPU Kernels with Branch Divergence
Research Manuscript Pillarsparse: Rethinking Unstructured Sparse Formats for Tensor Cores
Research Manuscript Deinfer: Efficient Parallel Inferencing for Decomposed Large Language Models
Research Manuscript CPA-BNN: A Secure and Efficient CIM and PUF Architecture for BNN Accelerator
Research Manuscript Integrated Timing-Driven Placement for Hybrid-Bonding-Based Face-to-Face 3D ICs
Research Manuscript A Locality-Aware Temporal Motif Mining Accelerator with Chunk-Based Search Tree Expansion
Research Manuscript An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference
Research Manuscript Dart: Towards Redundancy-Free RTL Simulation via DAG-Driven Execution
Research Manuscript Dypamear: Efficient and Scalable Dynamic Graph Pattern Mining on Practical Processing-in-Memory Architecture
Research Manuscript Fusedot: A Multiplication-Fused Dot Product Accelerator for Efficient LLM Inference
Research Manuscript Energyhdc: Intermittent Hyperdimensional Inference on Energy-Harvesting IoT
Research Manuscript NIAQ: Adaptive Non-Ideality-Aware Qubit Readout for Long-Term Accuracy
Engineering Presentation Accelerating X-State Aware Power Simulation Using Advanced Hardware Emulation
Engineering Presentation Local Layout Effect Coverage Check Using Artificial Neural Network-Based Surrogate Models
Engineering Presentation Past Present and Future of CDC & RDC Glitches: Improved Glitch Checker (IGC)
Research Manuscript L2L: Logic to Layout Exploration of Standard Cell Library Design
Research Special Session Weaving the Photonic Fabric: Electronic-Photonic Design Automation for Chiplet AI Systems
Research Manuscript DRCA: Reliable Bitwise Logic in DRAM via Dual-Rail Compute and Access
Taiwan
Research Manuscript AI Graces the Cell Party: Transformers, LLMs and Zero Drama Extraction
Research Manuscript Scalable and Adaptive Parallel Training of Graph Transformer on Large Graphs
Research Manuscript Weaver: Stratified Expert Scheduling for Memory-Constrained MoE Inference
Engineering Presentation From Design to Defense: Pioneering Pre-Silicon Leakage Detection for Novel ECC Crypto Core
Late Breaking Results Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond
Engineering Poster Gladiator Multi Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN Model
Engineering Presentation Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
Engineering Presentation Accurate Impact Modeling for Threshold Voltage Mismatch of Transistors in Same Chip
Research Manuscript Activity-Aware Partitioning for Effective Multi-Threaded Event-Driven RTL Simulation
Research Manuscript Attentioncap: Transformer Based Capacitance Matrix Learning Toward Full-Chip Extraction
Research Manuscript Autonomous Synthesis and Intelligent Optimization for Analog and RF Circuits
Research Manuscript Celle: Automated Standard Cell Library Extension via Equality Saturation
Research Manuscript Disentangled Differentiable Timing-Power Co-Optimization with Quad-Gradient Gate Sizing
Research Manuscript Epicell: Electro-Physical Co-Modeling for Standard Cell PPA Prediction
Research Manuscript Integrated Timing-Driven Placement for Hybrid-Bonding-Based Face-to-Face 3D ICs
Research Manuscript LATTE: Legality-Assured Differentiable Timing-Driven Detailed Placement
Research Special Session PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
Research Manuscript RM Poster Session Nine
Late Breaking Results Late Breaking Results: QUBO Approaches to Logic Equivalence Checking and Testing
Engineering Poster Slack-Exploiting Load Splitting for IR-Drop Mitigation
Research Manuscript LRTA: Routability-Driven 3D-Aware Track Assignment with Layer Reassignment
Engineering Presentation AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
Research Manuscript Leveraging AI for Silicon Health: Test, Yield & Fault Tolerance
Research Manuscript RM Poster Session Eight
Research Manuscript WFH-BFs: Dynamic Defense Against DNN Bit-Flips via a Weight Function Hierarchy
Research Manuscript An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference
Research Manuscript STAC: Spatial-Temporal Activation Contextualization for Resilient LLM Inference
Research Manuscript Brain-Like Hyper-Dimensional Graph Learning System with Hardware-Efficient Adaptive Sparsity
Research Manuscript Exquant: Global Expert Ranking–guided Mixed-Precision Quantization for Efficient MoE Inference
Research Manuscript GEMM-GS: Accelerating 3D Gaussian Splatting on Tensor Cores with GEMM-Compatible Blending
Research Manuscript SiTA: Exploiting Sparsity in Tensor-Product for Accelerating Quantum Readout Error Mitigation
Research Manuscript AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning
Research Manuscript LRTA: Routability-Driven 3D-Aware Track Assignment with Layer Reassignment
Research Manuscript iPCL-M: Pre-Training of Chip Layout for Metrics Evaluation and Optimization
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
Research Manuscript GEMIR: Graph-Based Joint Modeling of Electromigration and IR Drop for Power Grid
Research Manuscript WSC-Cost: An Accurate Cost Modeling Framework for Wafer-Scale Chips
Research Manuscript DRΛMA: Detailed Routing by a Versatile Maze Routing Algorithm
Research Manuscript ATOM-3D: Analytical Three-Dimensional Orientation-Aware Mixed-Size Placer
Research Manuscript iPCL-M: Pre-Training of Chip Layout for Metrics Evaluation and Optimization
Engineering Poster Gladiator 3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration
Research Manuscript Greenllm: SLO-Aware Dynamic Frequency Scaling for Energy-Efficient LLM Serving
Work in Progress STA Accuracy Validation: A Machine Learning Approach
Research Manuscript COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging
Research Manuscript G-Power: Architecture-Level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs
Research Manuscript Impart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning
Research Manuscript Operator-Level Acceleration for Sparse 3D Object Detection
Research Manuscript Towards Practical Live Migration for Heterogeneous Confidential Virtual Machines
Research Manuscript Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
Research Manuscript KL-MoE: A Hierarchical MoE Pruning Framework Exploiting KL Divergence
Research Manuscript LRTA: Routability-Driven 3D-Aware Track Assignment with Layer Reassignment
Research Manuscript Expcheck: Dynamic Expert-Aware Checkpointing for Mixture-of-Experts Based Models
Research Manuscript Mappingevolve: LLM-Driven Code Evolution for Technology Mapping
Research Manuscript OpenSUN: An Open Platform for Exploring Scale-Up Network Systems
Additional Meeting Open-Source EDA Birds-of-a-Feather Session
Research Manuscript RM Poster Session Three
Research Manuscript Winning the Token-Time Wars: Low-Bit LLMs, Faster MoE, and KV-Cache Systems
Research Manuscript TOPCELL: Topology Optimization of Standard Cell via LLMs
Research Manuscript Ciphershield: Safeguarding DNN Inputs from Ciphertext Side-Channels in TEE
Late Breaking Results Neural Subgraph Matching for Hardware Decompilation in Gate-Level Netlists
Research Manuscript Energyhdc: Intermittent Hyperdimensional Inference on Energy-Harvesting IoT
Engineering Special Session The Heterogeneous Future of Agentic AGI: Challenges and Opportunities!
Research Manuscript Exploiting Function-Family Structure in Analog Circuit Optimization
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript WFH-BFs: Dynamic Defense Against DNN Bit-Flips via a Weight Function Hierarchy
Research Manuscript HW-Router: Hardware-Aware Routing for Scalable Multi-LLM Serving
Research Manuscript Securerouter: Encrypted Routing for Efficient Secure Inference
Research Manuscript Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge
Research Manuscript CHiRM-DSE: CodeLLM-Based Hierarchical and Rule-Mining Guided DSE for FPGA Accelerators
Research Manuscript Crystal-KV: Efficient KV Cache Management for Chain-of-Thought LLMs via Answer-First Principle
Research Manuscript Efficient HLS Accelerator Floorplan on Multi-Die FPGA Aided by Graph Neural Networks
Research Manuscript Idealsim: Efficient Ideal Scenario Modeling for Processor Upper-Bound Performance Analysis
Late Breaking Results Late Breaking Results: Astfusion -- Two-Stage Structural Enhancement Learning for Robust HLS Code Generation
Late Breaking Results Late Breaking Results: Efficient MoE-ViT Gating on Edge Accelerator via Dynamic Expert Routing and Quantized Router
Late Breaking Results Late Breaking Results: HUSH: Silencing Inter-Core Interference in Real-Time Cache Analysis
Work in Progress Late Breaking Results: Micro-Dense Tensor-Core-Aligned N:M Sparse Kernel for Efficient Inference Acceleration
Late Breaking Results Late Breaking Results: Recoverability-Guided Layer-Wise N:M Sparsity Under Latency Constraints
Research Manuscript Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
Research Manuscript SpArC: Sparse Tensor Accelerator Compilation with Scheduling and Mapping
Engineering Poster Design Verification Automation (DVA) for PCB Signal and Power Integrity
Late Breaking Results Late Breaking Results: Power Mesh Construction for 3D-IC with Backside Power Delivery
Research Manuscript AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning
Research Manuscript DRCGen: A Controllable DRC Violation Case Generator with Cross-PDK Transferability for Rule-Deck and Tool Validation
Research Manuscript GPU-Fuzz: Finding Memory Errors in Deep Learning Frameworks
Research Manuscript COLA: Enabling Low-Latency Reads for Flash-Based SSDs via Code Length Adaptation
Research Manuscript LATTE: Legality-Assured Differentiable Timing-Driven Detailed Placement
Late Breaking Results Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond
Engineering Presentation AI-Enabled EDA Cloud Infrastructure and Design Optimization for Next-Generation Semiconductor Design
Research Manuscript Hero: Adaptive Orchestration of Retrieval-Augmented Generation on Heterogeneous Mobile SoC
Research Manuscript MIRAGE: Runtime Scheduling for Multi-Vector Image Retrieval with Hierarchical Decomposition
Research Manuscript OpenSUN: An Open Platform for Exploring Scale-Up Network Systems
Research Manuscript Stone-Skimming: Attacking Big-Data Analytics Applications with Page Table Walk
Engineering Poster Gladiator 3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Late Breaking Results Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond
M
Engineering Presentation Deep Reinforcement Learning Paradigm for Analog Design Automation
Engineering Poster ECO Strategy for BIG DIE SOC Convergence
Research Manuscript Energy-Efficient AI Systems - Cross-Stack Co-Design from Edge to Cloud
Research Manuscript RM Poster Session Four
Research Manuscript Etherssd: An In-Storage Ethereum Analytics Platform with Minimized I/O and Authentication Overhead
Research Manuscript PIMGRAG: A Heterogeneous PIM Architecture for Graph-Based Retrieval-Augmented Generation
Research Manuscript SpecANNS: Accelerating Graph-Based Approximate Nearest Neighbor Search with Speculative In-Storage Computing
Research Manuscript TierANNS: Scalable Graph-Based ANNS with CXL-Enabled Tiered Data Placement
Engineering Poster Efficient Power Management in USB4 Routers
Research Manuscript FBS: Accelerating CNN Inference over RNS-CKKS with Fewer Bootstrapping Sparsity
Research Manuscript Throughput-Oriented Speculative Decoding via Intra-Device Parallelism
Research Manuscript Cupilot: A Strategy-Coordinated Multi-Agent Framework for CUDA Kernel Evolution
Research Manuscript CPA-BNN: A Secure and Efficient CIM and PUF Architecture for BNN Accelerator
Research Manuscript Accshield: Operator-Aware Robust Scheduling for Fault-Tolerant AI Accelerators
Research Manuscript Coordinated Clip-Wise Gradient Scheduling for Full-Chip ILT via Policy Learning
Research Manuscript Scalable and Adaptive Parallel Training of Graph Transformer on Large Graphs
DAC Pavilion Panel What Are VCs Looking for at DAC?
Engineering Presentation Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper Generation
Engineering Poster The Pursuit of Golden Specification: Leveraging Architecture Formal
Engineering Presentation Architectural Coverage Analysis and ML-Based Automated-Test Generation
Research Manuscript LATTE: Legality-Assured Differentiable Timing-Driven Detailed Placement
Engineering Presentation Automated Validation of Liberty Models
Engineering Poster Adaptive Multi-Agent Framework for Automated Constraint Generation
Engineering Poster Gladiator Sigma Profiling: Profiling Solution for Power Integrity Signoff
Engineering Poster Mixed Transistor Design Closure
Engineering Poster Silicon Correlation of Voltage Droop Mitigation Scheme
Engineering Poster Accelerating Full Flat EMIR Sign-Off in Multi-Billion Instance
Engineering Poster Gladiator A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs
Engineering Poster Design Rule Checking for Rigid-Flex PCB
Engineering Presentation AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
Engineering Presentation A Probe-Based Time-Domain Methodology for Dynamic Thermal Management in Stacked-Die Architectures
Engineering Presentation Early Thermal Analysis and Silicon Correlation for Face-to-Face 3DIC Physical Design
Research Manuscript Etherssd: An In-Storage Ethereum Analytics Platform with Minimized I/O and Authentication Overhead
Research Manuscript Freebit: Unleashing the Performance Potential of Low-Bit LLMs Through PIM
Research Manuscript PIMGRAG: A Heterogeneous PIM Architecture for Graph-Based Retrieval-Augmented Generation
Research Manuscript TRIDENT: An End-to-End Streaming Accelerator for TriSpGEMM
Research Manuscript KERV: Kinematic-Rectified Speculative Decoding for Embodied VLA Models
Engineering Presentation Optimizing Reliability EM Sign-Off for 2nm Mobile SoCs
Engineering Special Session Using Quantum to Design Better Qubits: Engineering the Path from Lab to Scalable Systems
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
Research Manuscript Unlocking Automated Datapath Gating via Machine Learning Power Prediction
Research Manuscript Raise the Shields: A Modular RISC-V Extension for Post Quantum Cryptography
Research Manuscript Raise the Shields: A Modular RISC-V Extension for Post Quantum Cryptography
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Work in Progress SPICEMixer - Netlist-Level Circuit Evolution
Engineering Poster Achieving High-Integrity Safety for 360-Degree Automotive Display Soc's RETIME-IP: A Static Analysis Approach to ASIL-D Compliance
Engineering Poster INTENT-AWARE RDC ANALYSIS USING MINIMALLY BOOLEAN REASONING
Research Manuscript KERV: Kinematic-Rectified Speculative Decoding for Embodied VLA Models
Research Manuscript Runtime-ADAR: Runtime Anomaly Detection and Attack Recovery in Encrypted DNNs
Research Manuscript Exploiting Function-Family Structure in Analog Circuit Optimization
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
Engineering Presentation Lint-Free: A Generative AI Approach to Large Scale Autonomous RTL-Lint Correction
Research Manuscript Foundations and Frontiers: Bridging Traditional EDA and Generative AI
Research Manuscript Path-Based Timing Analysis Acceleration via Segment-Level Timing Arc Reuse
Research Manuscript RM Poster Session One
Research Manuscript TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
Research Manuscript Celle: Automated Standard Cell Library Extension via Equality Saturation
Research Manuscript CPA-BNN: A Secure and Efficient CIM and PUF Architecture for BNN Accelerator
Research Manuscript Athena: Analytical Timing-Aware Pre-Silicon Estimation of Side-Channel Leakage
Work in Progress SNN Accelerator Testing via Sparse Test Matrices
Research Manuscript Unlocking Automated Datapath Gating via Machine Learning Power Prediction
Engineering Presentation Automated Validation of Liberty Models
Research Manuscript Floquet-Based Subspace Projection Method for Time-Domain PPV Computation
Research Manuscript Legend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
Engineering Presentation Adaptive AI and Additive AI Techniques for High-Sigma Standard Cell Verification
Engineering Poster Library PPA DTCO with Library Profiler
Engineering Presentation From Design to Defense: Pioneering Pre-Silicon Leakage Detection for Novel ECC Crypto Core
Research Manuscript Hierarchical Boundary Recovery: Overcoming Synthesis Obscurity via SAT Sweeping
Research Manuscript L2L: Logic to Layout Exploration of Standard Cell Library Design
Engineering Presentation Design Spec to Die-Size Estimation Using ML Based Framework for Automotive SoCs
Engineering Presentation Design Spec to Die-Size Estimation Using ML Based Framework for Automotive SoCs
Research Manuscript KL-MoE: A Hierarchical MoE Pruning Framework Exploiting KL Divergence
Research Manuscript ENACT: Ensemble Neural Fields for Reactive Robot Control
Research Manuscript RM Poster Session Four
Engineering Presentation Past Present and Future of CDC & RDC Glitches: Improved Glitch Checker (IGC)
Engineering Poster A Scalable Timing Analysis and Closure Methodology for Ultra-Large Designs
Research Special Session Satreg: Regression-Based Neural Architecture Search for Lightweight Satellite Image Segmentation
Engineering Presentation Hardening Security of HW IPs by Verifying Their Negative Space Formally
Research Manuscript Leveraging AI for Silicon Health: Test, Yield & Fault Tolerance
Research Manuscript Interconnect-Driven System Architecture Innovation
Engineering Poster Risk Analysis for Chiplets, and Security Architecture
Engineering Poster Gladiator Multi Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN Model
Engineering Presentation Screening Analog Anomality for Security Vulnerability in Digitally Verified Crypto Cores
Engineering Presentation Crosstalk Effect Prediction and Optimization for Detail Routing Using CNN Models and Reinforcement Learning Flow Framework
Engineering Poster Crosstalk Hotspot Map Creation at Placement Stage Using CNN UNET Prediction Model
Engineering Presentation Structure Aware Clock Tree Synthesis Using Width-Driven CTS Cell Constraints
Engineering Poster Routability Optimizing Methodology Using Flexible Pin
Late Breaking Results Automated Design of Device Fingerprinting Circuits for FPGAs
Engineering Poster Fair Play in the Multiplex: Formal Verification of Complex Arbmux Designs
Research Manuscript Notsotiny: A Large, Living Benchmark for RTL Code Generation
Research Manuscript Sparsity- and Tolerance-Aware Temporally Redundant Neural Networks
Research Manuscript Chimera: A Unified FHE Accelerator with Enhanced Compatibility for TFHE
Research Manuscript UniNL: Unifying Fragmented Non-Linear Operators for Efficient Edge LLM Inference
Engineering Special Session Bridging Physics and Engineering: Quantum EDA for Superconducting Qubits and Amplifiers
Engineering Presentation BIMEM-RAG: Reinforced Dual Memory Retrieval with Bidirectional Reasoning for RTL Synthesis and Summarization
Engineering Poster Gladiator Cost-Based Partial Subgraph Matching for Circuit Pattern Recognition
Engineering Presentation Graph Isomorphism for Explainable Transistor-Level Circuit Comparison
Research Manuscript CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
Engineering Presentation Analysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous Integration
Engineering Presentation Lint-Free: A Generative AI Approach to Large Scale Autonomous RTL-Lint Correction
Engineering Poster Hierarchical Cost-Efficient IR Methodology for AI SoCs
DAC Pavilion Panel From RTL to Reality: Building Security into the Silicon Lifecycle
N
Engineering Poster A Scalable Timing Analysis and Closure Methodology for Ultra-Large Designs
Engineering Poster Channel Width Optimization for IR Drop Reduction in Advanced SoCs
Research Manuscript ARC-SRAM: A Memory Subarray with Local Addressing and Reduced Access Energy
Engineering Poster INTENT-AWARE RDC ANALYSIS USING MINIMALLY BOOLEAN REASONING
Engineering Poster Gladiator Multi Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN Model
Engineering Presentation Screening Analog Anomality for Security Vulnerability in Digitally Verified Crypto Cores
Research Manuscript RM Poster Session Seven
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Engineering Presentation Scalable Verification Methodology for Stacked 3D Chiplet-Based Designs Using SIP Flow
Engineering Presentation Analysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous Integration
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Research Manuscript RM Poster Session Five
DAC Pavilion Panel Is EDA AI Delivering on Its ROI Promise?
Engineering Special Session AI and Digital Techniques Powering the Future of Analog Design
Research Manuscript Pioneering AI and GPU-Powered Techniques for Advanced Timing Analysis and Optimization
Research Manuscript RM Poster Session One
Engineering Poster New Thermal Analysis Workflow for 3DIC Designs
Engineering Presentation Designing Power- and Area-Efficient Custom NPUs for Edge AI
DAC Pavilion Panel Build vs Buy: Who Owns the Intelligence Behind Tomorrow's Chips?
Engineering Poster Gladiator Accurate Full-Custom Thermal and EM Analysis for Advanced Nodes
Research Manuscript RAM-CGRA: Reachability-Aware Mapping for CGRAs
Research Manuscript RM Poster Session Six
Research Manuscript Revolutionizing Synthesis Flows
Research Manuscript REACT: Rapid Error-Tolerant Activation Compressor for Efficient Transformer Training
Research Manuscript Vten: Tensor-Centric Verification Framework for Domain-Specific Accelerators
Research Manuscript CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
Research Manuscript CPA-BNN: A Secure and Efficient CIM and PUF Architecture for BNN Accelerator
Research Manuscript KL-MoE: A Hierarchical MoE Pruning Framework Exploiting KL Divergence
Research Manuscript PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
Research Manuscript TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Special Session AI and Multi‑die: A Reinforcing Cycle
Research Manuscript TRIDENT: An End-to-End Streaming Accelerator for TriSpGEMM
Research Manuscript Advances in 3D/2.5D Physical Design
Research Manuscript Light-Bound Transformers: Hardware-Anchored Robustness for Silicon-Photonic Computer Vision Systems
Research Manuscript RM Poster Session Two
Engineering Special Session Spec-Tacular! Reinventing Design Specifications with AI
Research Special Session Quantum Stack Attack: Building the Machine
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
Engineering Special Session Gaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect?
Engineering Special Session Gaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect?
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Engineering Presentation Advancing Silicon Lifecycle Management with Embedded Trace
Late Breaking Results Automated Design of Device Fingerprinting Circuits for FPGAs
Engineering Special Session AI and Multi‑die: A Reinforcing Cycle
Engineering Special Session AI and Multi‑die: A Reinforcing Cycle
Research Manuscript Decoding the Past: Recovering Sensitive Data from SRAM Aging Imprints
United States of America
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Work in Progress Accelerating Functional Fault Grading for Flash and DRAM Designs
Engineering Presentation Adaptive QoS Optimization for SoC Performance Enhancement Using Dueling Double Deep Q-Networks
Research Manuscript SCOUT: Thermal-Aware SRAM Allocation for Real-Time DNN Tasks on Edge TPU
Research Manuscript Sparsity- and Tolerance-Aware Temporally Redundant Neural Networks
Research Manuscript ENACT: Ensemble Neural Fields for Reactive Robot Control
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Engineering Presentation Staged Snapshots for Firmware-Hardware Collaborative Debug
Research Manuscript Freebit: Unleashing the Performance Potential of Low-Bit LLMs Through PIM
P
Engineering Presentation Comprehensive Physical Verification Approach for Heterogeneous 2.5/3D Integration
Engineering Poster Channel Width Optimization for IR Drop Reduction in Advanced SoCs
Exhibitor Forum BRONCO AI: Introducing Dvbench: A Production-Grade Benchmark for Design Verification AI
Engineering Special Session Spec-Based Acceleration fo Design Verification From Start to Finish
TechTalk Towards a Fully AI-Native EDA Stack
China
China
Engineering Presentation Clean Implementations - Untangle the Distractions with Zen Insights
Engineering Presentation Efficient Routing and Connectivity Repair for Large-Scale Hierarchical Metal Networks
Engineering Poster Free Hand Routing- Sketch to Layout
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
Engineering Presentation UVM-MS: A Novel Approach to Mixed-Signal IP Verification
Engineering Presentation Using Arm Native Acceleration with VLAB Virtual Platforms
Engineering Poster New Thermal Analysis Workflow for 3DIC Designs
Engineering Presentation Staged Snapshots for Firmware-Hardware Collaborative Debug
Research Manuscript Notsotiny: A Large, Living Benchmark for RTL Code Generation
Research Manuscript Flip-FET-Based VLSI Design Framework with Congestion-Aware Dual-Side Routing
Engineering Presentation Adaptive QoS Optimization for SoC Performance Enhancement Using Dueling Double Deep Q-Networks
Research Manuscript ARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing
Engineering Poster Low Power Optimization Through Fast and Accurate Time-Based Power Analysis
Research Manuscript Semi-Virtual Addressing to Enhance Memory Safety on Microcontrollers
Engineering Poster Low Power Optimization Through Fast and Accurate Time-Based Power Analysis
Engineering Poster Revisiting PDN at the MOL Boundary: A Placement-Aware Power Delivery Flow
Engineering Poster Routability Optimizing Methodology Using Flexible Pin
Research Manuscript Differentiable Fill Insertion with Explicit Delay Optimization
Research Manuscript Flip-FET-Based VLSI Design Framework with Congestion-Aware Dual-Side Routing
Engineering Poster SLC-Based Real-Time Traffic Buffering with DRAM Row-Aware Write Back
Engineering Poster Low Power Optimization Through Fast and Accurate Time-Based Power Analysis
Engineering Presentation Local Layout Effect Coverage Check Using Artificial Neural Network-Based Surrogate Models
Research Manuscript Test Point Insertion with ATPG-Free Self-Supervised Learning
Engineering Special Session AI and Multi‑die: A Reinforcing Cycle
Engineering Presentation AI-Assisted EDA Tools Development
Engineering Presentation Enabling AI Agent Flows for Verification Triage & Debug
Engineering Presentation Morph-Inspect: Structural Assurance for Inserted Logic
Engineering Poster SELECT: Sensitivity Based Exploration and Localisation of Event-Wise Correlated Tokens for Test Generation
Engineering Presentation STEER: Simulation of Templates Engine for Efficient Resource Usage
Engineering Special Session The Next Decade of Semiconductors And Transformation Through Industry, Academia, and Government
Engineering Poster Gladiator A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs
Engineering Poster TAWT: Towards Autonomous Wrapper Tuning
Engineering Special Session Digital Inside Analog: Continuous-Time Pipelined ADCs for Wideband Analog-to-Digital Conversion
Engineering Poster Gladiator Outsmarting State Space Complexity Through Proven Reset Abstraction Stratergies
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
Research Manuscript KL-MoE: A Hierarchical MoE Pruning Framework Exploiting KL Divergence
Research Manuscript Celle: Automated Standard Cell Library Extension via Equality Saturation
Engineering Presentation AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
Late Breaking Results Late Breaking Results: Power Mesh Construction for 3D-IC with Backside Power Delivery
Research Manuscript Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells
Research Manuscript Cell-Structure-Independent Transistor-Level Placement and MOL-Aware Routing Framework Beyond the Standard-Cell Paradigm
Late Breaking Results Late Breaking Results: A Coarse-to-Fine PCB Placement Framework via LLM-Guided Component Grouping and Group-Aware Placement
Engineering Presentation An Adjustable Length Compression Method for MBIST Repair Information
Research Manuscript Differentiable Dreams: GPU-Powered Litho Gets Its Gradient Groove Back
Engineering Poster Maximize RoI Through Glitch Power Optimization at Early Design Stage
Additional Meeting Additional Meeting - SIGDA Vision 2030 Town Hall
Research Manuscript RM Poster Session Six
Research Manuscript Raise the Shields: A Modular RISC-V Extension for Post Quantum Cryptography
Research Manuscript Efficient & Edge-Ready AI Systems
Research Manuscript Hyperlidar: Adaptive Post-Deployment LiDAR Segmentation via Hyperdimensional Computing
Research Manuscript RM Poster Session Six
Engineering Presentation A Programmable, Synthesizable CMOS Analog Optimization IP Core for Real-Time Control
Engineering Presentation AI-Assisted EDA Tools Development
Engineering Presentation Enabling AI Agent Flows for Verification Triage & Debug
Engineering Poster FPGA-to-ASIC Conversion via Hierarchical Wrapping
Engineering Presentation Morph-Inspect: Structural Assurance for Inserted Logic
Research Manuscript RM Poster Session Nine
Engineering Presentation No Credit Where Credit Is Due: Quiesced Formal Check for PCIe Crediting
Research Special Session Progress and Roadmap Toward an Automated EDA R&D Engineer
Research Manuscript Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
Engineering Presentation Efficient IR-Aware Powergrid Optimization
Research Manuscript Parallelizing Complementary Approximate Reachability
Research Manuscript CPA-BNN: A Secure and Efficient CIM and PUF Architecture for BNN Accelerator
Engineering Presentation Formally Validating Industry Standard BCH‑ECC/CRC Codes – A Step by Step Recipe
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Research Manuscript An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference
Research Manuscript Inferweave: Efficient LLM Inference on the MT-3000 Processor
Research Manuscript Flowplace: Flow Matching for Chip Placement
Research Manuscript How Can Reinforcement Learning Achieve Expert-Level Placement?
Research Manuscript Integrated Timing-Driven Placement for Hybrid-Bonding-Based Face-to-Face 3D ICs
Research Manuscript Amoeba: Runtime Tensor Parallel Transformation for LLM Inference Services
Research Manuscript OpenSUN: An Open Platform for Exploring Scale-Up Network Systems
Research Manuscript PRS: An Efficient Parallel SAT Framework
Research Manuscript NVLLM: A 3D NAND-Centric Architecture Enabling Edge on-Device LLM Inference
Research Manuscript Lhgstore: An In-Memory Learned Graph Storage for Fast Updates and Analytics
Research Manuscript CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
Research Manuscript RM Poster Session Six
Research Manuscript Silicon’s Last Stand: Defending Against Quantum and Architectural Decay
Research Manuscript UniNL: Unifying Fragmented Non-Linear Operators for Efficient Edge LLM Inference
Research Manuscript DRCA: Reliable Bitwise Logic in DRAM via Dual-Rail Compute and Access
China
China
Research Manuscript Emudrop: A Minimalistic, Hardware-Based Emulation Detection Approach Through Intel Reserved Opcodes
Research Manuscript PMU-Faker: The Apparently Harmless Performance Monitoring Unit Events Are Actually Harmful
Research Manuscript Seeing the Unseen: Reverse Engineering Hidden PMU Events by Differential Analysis and Simulation Validation
Research Manuscript Unveiling the Security Risks Driven by the Hardware Interrupts
Research Manuscript iPCL-M: Pre-Training of Chip Layout for Metrics Evaluation and Optimization
Research Manuscript Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge
Late Breaking Results Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond
Research Manuscript PMU-Faker: The Apparently Harmless Performance Monitoring Unit Events Are Actually Harmful
Research Manuscript Seeing the Unseen: Reverse Engineering Hidden PMU Events by Differential Analysis and Simulation Validation
Research Manuscript Unveiling the Security Risks Driven by the Hardware Interrupts
Research Manuscript Parallel Combinational Equivalence Checking Through Factored Form Sharing
Engineering Presentation Hunting RTL Glitches Before They Burn Power: A Practical RTL Success Story
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Engineering Presentation Efficient Power Modeling of Multi-Domain Clock Gating Circuits
Research Manuscript RM Poster Session One
Engineering Special Session Gaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect?
Engineering Special Session The Heterogeneous Future of Agentic AGI: Challenges and Opportunities!
Engineering Poster Accelerating Full Flat EMIR Sign-Off in Multi-Billion Instance
Research Manuscript LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout
Engineering Poster A Real-Time Metric‑Driven Scorecard for Quantifying and Benchmarking Physical‑Design Quality and Deployment Progress
Engineering Presentation Advanced Automation Framework for Clock and Reset Management in SoC Designs – Bridging Design Intent, Verification, Test and Implementation
Engineering Presentation Advanced Hard IP Integration Requirement Extraction and Checker
Engineering Poster Advanced Hard IP Integration Requirement Extraction and Checker
Engineering Presentation AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
Research Manuscript Attackonctf: Defending Hardware Security Competition Benchmarks in the Age of LLMs
Research Manuscript RM Poster Session Three
Research Manuscript Hidden in Plain Sight: Designing Systems for Private Intelligence
Work in Progress Late Breaking Results: Encoding-in-Memory via Generating True Random One-Time Password
Research Manuscript RM Poster Session One
Engineering Poster Gladiator Sigma Profiling: Profiling Solution for Power Integrity Signoff
Engineering Special Session AI and Multi‑die: A Reinforcing Cycle
DAC Pavilion Panel Build vs Buy: Who Owns the Intelligence Behind Tomorrow's Chips?
Engineering Poster Multi-Cycle Dynamic Vectorless Analysis for Improved PDN Signoff
Engineering Poster Design Rule Checking for Rigid-Flex PCB
Research Manuscript DRCA: Reliable Bitwise Logic in DRAM via Dual-Rail Compute and Access
Engineering Presentation IP Design for Mixed-Signal and High-Speed SoCs
Research Manuscript Intelligent Systems for Physical & Structured Worlds
Engineering Poster Gladiator A Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance Nodes
Engineering Presentation Automated Validation of Liberty Models
Engineering Poster Liberty-Based Profiling for IP Benchmarking
Engineering Presentation A Unified QA Framework for Intel Library Validation Using Siemens Solido Crosscheck
Engineering Poster Hierarchical Cost-Efficient IR Methodology for AI SoCs
Engineering Poster Track Analyzer + Visualizer
Engineering Poster Fair Play in the Multiplex: Formal Verification of Complex Arbmux Designs
Research Manuscript Decoding the Past: Recovering Sensitive Data from SRAM Aging Imprints
Engineering Presentation Hardening Security of HW IPs by Verifying Their Negative Space Formally
Research Manuscript Athena: Analytical Timing-Aware Pre-Silicon Estimation of Side-Channel Leakage
Engineering Poster Gladiator A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs
Engineering Presentation A Service-Aware Energy-Efficient DVFS Framework for System-on-Chip Architectures
Engineering Special Session Gaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect?
Research Manuscript Delay-Constrained Area Optimisation Using SAT-Based Local Improvement
Engineering Poster Efficient Power Management in USB4 Routers
Research Manuscript Throughput-Oriented Speculative Decoding via Intra-Device Parallelism
Research Manuscript Credix: A Credit-Driven Distributed Buffer Management for Large-Scale Switching Chips
Research Manuscript Per Flow Asynchronous Traffic Shaping in Time Sensitive Networking
Research Manuscript Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC
Research Manuscript Hyspecpro: Scalable Hypergraph Partitioning via Spectral Projection Optimization
Research Manuscript LATTE: Legality-Assured Differentiable Timing-Driven Detailed Placement
Research Manuscript PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
Research Manuscript Pushing the Limits of Inverse Lithography with Generative Reinforcement Learning
Research Manuscript Schemacoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting
Research Manuscript TOPCELL: Topology Optimization of Standard Cell via LLMs
Late Breaking Results Late Breaking Results: HUSH: Silencing Inter-Core Interference in Real-Time Cache Analysis
Research Manuscript Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
Research Manuscript Graph-Based Attack-Chain Traceback Across Multiple In-Vehicle Network Domains
Research Manuscript ISA-PM: A Unified ISA Extension and Microarchitecture Enabling Efficient ECPM in IoT Devices
China
Research Manuscript Towards Practical Live Migration for Heterogeneous Confidential Virtual Machines
Research Manuscript Celle: Automated Standard Cell Library Extension via Equality Saturation
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Presentation Beyond the Block: Verifying Complex Systems in Context
Research Manuscript BREW-RC: Bit-Exact Recovery of ECCs from Write Timing in ReRAM Crossbars
Engineering Special Session Capturing Quantum Components in Quantum EDA
Engineering Poster Accelerating Full Flat EMIR Sign-Off in Multi-Billion Instance
Engineering Special Session Gaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect?
Engineering Presentation Enabling PSS-Driven Early SoC Verification By Enriching IP-XACT Information
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
Engineering Poster Central DMA IP Verification Using Layered UVM Scoreboard
Research Manuscript Architectures for AI of Many Shapes
Late Breaking Results Late Breaking Results: ROAST: Reverse-Training Offset Attack on Spatial Sampling Topologies
Work in Progress Late Breaking Results: Tiny Brain, Big World: Autonomous MCU-Friendly Navigation for Mapless Dynamic Environments
Research Manuscript Light-Bound Transformers: Hardware-Anchored Robustness for Silicon-Photonic Computer Vision Systems
Research Manuscript WINNER: A Wireless In-Vivo/ex-Vivo Runtime Analyzer for Intermittent Computing
Engineering Special Session AI for Specifications Across the Stack: Formalization, Alignment, Reconstruction, and Handoff
Engineering Poster Vmin Reliability Through Critical Path-Aware PDN Analysis
Late Breaking Results Late Breaking Results: Fisher-Guided Selective Error Reconstruction for Quantized LLMs
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Engineering Presentation Custom Implementation of High-Speed Digital Blocks Using Virtuoso Studio
Engineering Presentation Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
Engineering Poster INTENT-AWARE RDC ANALYSIS USING MINIMALLY BOOLEAN REASONING
Engineering Presentation Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper Generation
Engineering Presentation AI-Assisted EDA Tools Development
Engineering Presentation Enabling AI Agent Flows for Verification Triage & Debug
Engineering Poster FPGA-to-ASIC Conversion via Hierarchical Wrapping
Engineering Presentation Morph-Inspect: Structural Assurance for Inserted Logic
Engineering Presentation Staged Snapshots for Firmware-Hardware Collaborative Debug
Engineering Poster Novel Approach to Signoff Large MRAM Memory IP Using Hierarchical Flow
Engineering Presentation A Programmable, Synthesizable CMOS Analog Optimization IP Core for Real-Time Control
Engineering Poster ECO Strategy for BIG DIE SOC Convergence
Engineering Poster Free Hand Routing- Sketch to Layout
Research Manuscript Sparsity- and Tolerance-Aware Temporally Redundant Neural Networks
Research Manuscript Sparsity- and Tolerance-Aware Temporally Redundant Neural Networks
Research Special Session Innovations for the Next Frontier: Space Edge AI and Orbital Data Centers
Research Manuscript RM Poster Session Eight
Engineering Poster Novel Approach to Signoff Large MRAM Memory IP Using Hierarchical Flow
Engineering Poster A Simple and Predictable Solution for Early Full-Chip LVS Convergence
Engineering Poster Adaptive Multi-Agent Framework for Automated Constraint Generation
Engineering Poster Gladiator Sigma Profiling: Profiling Solution for Power Integrity Signoff
Engineering Presentation Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
Engineering Presentation Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper Generation
Engineering Poster Automatic SDC Creation for Static Timing Analysis
Engineering Poster Hierarchical IP Block Resizing on the Fly
Engineering Poster Library PPA DTCO with Library Profiler
Research Manuscript BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis
Research Special Session LLM for EDA in Front-End Design: Challenges and Opportunities
Late Breaking Results Late Breaking Results: "describing" Your Way to a Functional Microfluidic Chip
Work in Progress Late Breaking Results: A Scalable and Efficient Multi-Layer 3D-Printed Microfluidic Design Synthesis
Research Manuscript Delay-Constrained Area Optimisation Using SAT-Based Local Improvement
Research Manuscript WINNER: A Wireless In-Vivo/ex-Vivo Runtime Analyzer for Intermittent Computing
Research Manuscript Stateful Embedded Fuzzing Using Peripheral-Accurate Systemc Virtual Prototypes
Engineering Poster A Scalable Timing Analysis and Closure Methodology for Ultra-Large Designs
Research Manuscript Sparsity- and Tolerance-Aware Temporally Redundant Neural Networks
Engineering Presentation Analysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous Integration
Engineering Poster Revisiting PDN at the MOL Boundary: A Placement-Aware Power Delivery Flow
Engineering Poster Routability Optimizing Methodology Using Flexible Pin
Work in Progress SPICEMixer - Netlist-Level Circuit Evolution
Engineering Special Session Challenges and Solutions in the next-Generation Emulation and Prototyping Solutions
Research Manuscript Closing the Loop: Hybrid NAS Guided by Analytical and Hardware-Calibrated Quantum Cost Modeling
Work in Progress Late Breaking Results: A Neuromorphic Accelerator for Efficient Multi-Head Attention Processing in Spiking Vision Transformers
Work in Progress Late Breaking Results: A Resource-Constrained Co-Design Framework for Enabling Heterogeneous Quantum Chiplet Ensembles via Circuit Cutting
Work in Progress Late Breaking Results: Energy-Aware Scheduling of Open-Vocabulary Detection on Low-Power Mobile Robots
Late Breaking Results Late Breaking Results: Hardware-Aware Compilation Reshapes Trainability in Variational Quantum Circuits
Late Breaking Results Late Breaking Results: Hardware-Efficient Quantum Reservoir Computing via Quantized Readout
Work in Progress Late Breaking Results: Quantum-Aware Model Compression Techniques for Scalable Quantum Machine Learning
Research Manuscript Netdetox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration
Research Special Session Co-Designed Compute Memories for Ultra-Efficient DNN Inference
DAC Pavilion Panel Build vs Buy: Who Owns the Intelligence Behind Tomorrow's Chips?
Engineering Poster Gladiator Outsmarting State Space Complexity Through Proven Reset Abstraction Stratergies
Research Manuscript NVLLM: A 3D NAND-Centric Architecture Enabling Edge on-Device LLM Inference
Research Manuscript Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
Research Manuscript Gwrite: Offloading Replication in Disaggregated Memory Systems
Research Manuscript SSD Reforge: Dynamic Parity Management to Extend SSD Lifetime Under Aging
Research Manuscript HyPAS: A Hybrid Optimization Framework for Placement and Sizing Co-Optimization
Engineering Presentation ANA-MODELGEN: Automating Analog IP Model Generation and Validation for Efficient Mixed-Signal Verification
Engineering Presentation UVM-MS: A Novel Approach to Mixed-Signal IP Verification
Engineering Poster Solving Memory Subsystem Verification Challenges for Multi-Instance Designs
Engineering Presentation A Programmable, Synthesizable CMOS Analog Optimization IP Core for Real-Time Control
Engineering Poster INTENT-AWARE RDC ANALYSIS USING MINIMALLY BOOLEAN REASONING
Research Manuscript BREW-RC: Bit-Exact Recovery of ECCs from Write Timing in ReRAM Crossbars
Research Manuscript HyPAS: A Hybrid Optimization Framework for Placement and Sizing Co-Optimization
Research Manuscript Knowledge-Driven Hybrid SSD Management Enhanced by Fine-Tuned LLMs
Research Manuscript RM Poster Session Five
Research Manuscript Reflectbench: An Agentic Framework for Generating System-Level Design Testbench via Consensus and Reflection
Research Manuscript TierANNS: Scalable Graph-Based ANNS with CXL-Enabled Tiered Data Placement
Research Manuscript Achieving Intra- and Inter-Operator Communication Lower Bounds in Near-Memory Processing
Research Manuscript DRCA: Reliable Bitwise Logic in DRAM via Dual-Rail Compute and Access
Engineering Special Session Applying AI to Transform Specification-Driven Development and Engineering Productivity
Engineering Presentation Leveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.ai
Research Manuscript OpenSUN: An Open Platform for Exploring Scale-Up Network Systems
Research Manuscript GEMIR: Graph-Based Joint Modeling of Electromigration and IR Drop for Power Grid
Research Manuscript FBS: Accelerating CNN Inference over RNS-CKKS with Fewer Bootstrapping Sparsity
Research Manuscript EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation
Research Manuscript A Levelized Load-Balanced and Structure-Adaptive GPU LU Factorization Method for Circuit Simulation
Research Manuscript DiffDEG: Diffusion-Enhanced Design Evolution Graph Representation Learning for Post-Layout Optimization
Research Manuscript Path-Based Timing Analysis Acceleration via Segment-Level Timing Arc Reuse
Research Manuscript Accelerating AI+SAR Applications Through Enhanced Graph Optimization
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
Research Manuscript Flowplace: Flow Matching for Chip Placement
Research Manuscript How Can Reinforcement Learning Achieve Expert-Level Placement?
Research Manuscript Integrated Timing-Driven Placement for Hybrid-Bonding-Based Face-to-Face 3D ICs
Research Manuscript Runtime-ADAR: Runtime Anomaly Detection and Attack Recovery in Encrypted DNNs
Research Manuscript WFH-BFs: Dynamic Defense Against DNN Bit-Flips via a Weight Function Hierarchy
Research Manuscript Making Sense of Job Preemption for Distributed Deep Learning Acceleration
Engineering Poster Revisiting PDN at the MOL Boundary: A Placement-Aware Power Delivery Flow
Engineering Poster Revisiting PDN at the MOL Boundary: A Placement-Aware Power Delivery Flow
Engineering Poster Unifying Pre- and Post-Silicon Software Validation Through Modeling
Research Manuscript Tdsnap: Enabling Secure Function-as-a-Service with Trusted Domain Snapshots
Research Manuscript Adaptive Spiking Neural Networks for Real-Time Multi-Object Detection Tasks
Research Manuscript Stitch: Assertion-Guided Patching of On-Chip Protocol Implementations Using LLMs
Engineering Presentation Scalable Verification Methodology for Stacked 3D Chiplet-Based Designs Using SIP Flow
Research Manuscript Silicon Whisperers: When LLMs Learn to Speak RTL
Research Manuscript Marlin: I/O-Efficient Prefix KV Cache Retrieval for Long-Prefix LLM Serving
Research Manuscript Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
Research Manuscript DIA-CIM: A Dynamic Iterative Aggregation Graph Neural Network and Its Hardware Co-Design for Energy-Efficient Graph Processing
Research Manuscript HYPER-CIM: Hierarchical Predictive Exploration and Realizable Design Flow for High-Efficient Digital CIM
Research Manuscript Maple: Efficient Data-Transfer-Aware Mapping Exploration for NDP-Enabled Edge LLM Inference
Research Manuscript Cupilot: A Strategy-Coordinated Multi-Agent Framework for CUDA Kernel Evolution
Research Manuscript Hidden in Plain Sight: Designing Systems for Private Intelligence
Research Manuscript RM Poster Session Nine
Research Manuscript RM Poster Session One
Engineering Presentation Modeling and Optimization of Power MOSFET Device Layouts with Optislang Tool
Engineering Poster Design Rule Checking for Rigid-Flex PCB
Engineering Presentation Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper Generation
Engineering Poster Gladiator Agile Silicon: A Gitops-Based PD Orchestration Framework Enabling <10-Person PD Team to Deliver CPO Tapeouts
Engineering Poster Channel Width Optimization for IR Drop Reduction in Advanced SoCs
Engineering Poster A Compact Digital IP for FMCW Chirp Linearity Monitoring in Automotive Radar Systems
Engineering Poster An Adaptive Dynamic Power Reduction Technique for Digital Filters
Engineering Poster Free Hand Routing- Sketch to Layout
Engineering Presentation AI-Accelerated IP Libraries: From Optimization to Signoff
Engineering Presentation System & Software Design
Engineering Presentation UVM-MS: A Novel Approach to Mixed-Signal IP Verification
Engineering Presentation Design Spec to Die-Size Estimation Using ML Based Framework for Automotive SoCs
Engineering Presentation Efficient IR-Aware Powergrid Optimization
Engineering Presentation Design Spec to Die-Size Estimation Using ML Based Framework for Automotive SoCs
Engineering Poster Free Hand Routing- Sketch to Layout
DAC Pavilion Panel Is EDA AI Delivering on Its ROI Promise?
DAC Pavilion Panel From RTL to Reality: Building Security into the Silicon Lifecycle
DAC Pavilion Panel Build vs Buy: Who Owns the Intelligence Behind Tomorrow's Chips?
Research Special Session Modeling DWDM CPO Systems at Scale: Photonic-Electronic Co-Simulation for 100+ Tb/s Interconnects
Engineering Poster SHELL: AI-Driven UVM Framework
Research Manuscript Are We There Yet? That is the Question ... for Computing near and in Memory.
Research Manuscript RM Poster Session Seven
Engineering Presentation Efficient IR-Aware Powergrid Optimization
Engineering Poster Library PPA DTCO with Library Profiler
Research Manuscript ARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing
Engineering Poster Routability Optimizing Methodology Using Flexible Pin
Engineering Poster Real-Time Local Layout Effects Analysis for Advanced Design Optimization
Research Manuscript COLA: Enabling Low-Latency Reads for Flash-Based SSDs via Code Length Adaptation
Research Manuscript EASY-ZKP: An End-to-End FPGA-Accelerated System for Zero Knowledge Proofs
Research Manuscript TOPCELL: Topology Optimization of Standard Cell via LLMs
Engineering Poster Gladiator Sigma Profiling: Profiling Solution for Power Integrity Signoff
Research Manuscript Energy-Efficient AI Systems - Cross-Stack Co-Design from Edge to Cloud
Engineering Poster Reduced Order Modelling (ROM) Based Full Chip EMIR Signoff
Work in Progress Accelerating Functional Fault Grading for Flash and DRAM Designs
Research Manuscript Charting the Architecture of Tomorrow’s Fault Tolerant Quantum Machines by Harmonizing Codes to Systems
Work in Progress Late Breaking Results: Guiding Compiler Optimizations for Neutral Atom Quantum Computers Through Visualizations
Research Manuscript RM Poster Session Five
Research Manuscript Search Smarter, Not Harder: A Scalable, High-Quality Zoned Neutral Atom Compiler
Work in Progress Compact ML-Based Glitch Propagation Modeling of Standard Cells
Engineering Poster Design Verification Automation (DVA) for PCB Signal and Power Integrity
Engineering Poster Hierarchical IP Block Resizing on the Fly
Engineering Poster Pss–enabled Design Space Exploration for Energy Management Systems
Research Manuscript Expcheck: Dynamic Expert-Aware Checkpointing for Mixture-of-Experts Based Models
Research Manuscript Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
Research Manuscript Floquet-Based Subspace Projection Method for Time-Domain PPV Computation
Engineering Poster Multi-Cycle Dynamic Vectorless Analysis for Improved PDN Signoff
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Engineering Special Session The Heterogeneous Future of Agentic AGI: Challenges and Opportunities!
Engineering Poster Hierarchical IP Block Resizing on the Fly
Late Breaking Results Late Breaking Results: Fisher-Guided Selective Error Reconstruction for Quantized LLMs
Research Manuscript STAC: Spatial-Temporal Activation Contextualization for Resilient LLM Inference
Research Manuscript Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
Research Manuscript Celle: Automated Standard Cell Library Extension via Equality Saturation
Research Manuscript GenDSE: Generative CPU Design Space Exploration via Sequential Decision Making
Research Manuscript Maple: Efficient Data-Transfer-Aware Mapping Exploration for NDP-Enabled Edge LLM Inference
Research Manuscript OpenSUN: An Open Platform for Exploring Scale-Up Network Systems
Research Manuscript Weaver: Stratified Expert Scheduling for Memory-Constrained MoE Inference
Research Manuscript TOPCELL: Topology Optimization of Standard Cell via LLMs
Research Manuscript Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
Research Manuscript Weaver: Stratified Expert Scheduling for Memory-Constrained MoE Inference
Engineering Presentation Hunting RTL Glitches Before They Burn Power: A Practical RTL Success Story
Research Manuscript Compilation Tells Energy: Rethinking Power Modeling for DNN Accelerator Agile Design
Research Manuscript FUSE-TCAD: A Diffusion-Based Multi-Field Surrogate for High-Fidelity TCAD Device Simulation
Research Manuscript FreqSEM: Frequency-Aware High-Precision Contour Extraction for Lithographic SEM Images
Research Manuscript OpenSUN: An Open Platform for Exploring Scale-Up Network Systems
Research Manuscript Hero: Adaptive Orchestration of Retrieval-Augmented Generation on Heterogeneous Mobile SoC
Research Manuscript KERV: Kinematic-Rectified Speculative Decoding for Embodied VLA Models
Engineering Presentation Deep Reinforcement Learning Paradigm for Analog Design Automation
Engineering Poster New Thermal Analysis Workflow for 3DIC Designs
Engineering Presentation A Probe-Based Time-Domain Methodology for Dynamic Thermal Management in Stacked-Die Architectures
Engineering Presentation Multi-Cycle Interconnect Synthesis in Small to Large Cutting Methodology
Research Manuscript Architectures for AI of Many Shapes
Engineering Presentation Scalable Verification Methodology for Stacked 3D Chiplet-Based Designs Using SIP Flow
Research Special Session Analog Quantum Simulation on Google’s Willow Processor
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Research Special Session RBF-Driven Analog Neural Networks for Flexible Wearable Near-Sensor at the Extreme Edge
Engineering Poster Slack-Exploiting Load Splitting for IR-Drop Mitigation
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
Research Manuscript Sparsity- and Tolerance-Aware Temporally Redundant Neural Networks
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Engineering Poster Adaptive Multi-Agent Framework for Automated Constraint Generation
Engineering Presentation Advanced Hard IP Integration Requirement Extraction and Checker
Engineering Poster Advanced Hard IP Integration Requirement Extraction and Checker
Research Manuscript RM Poster Session Two
Research Manuscript RM Poster Session Three
Research Manuscript Floquet-Based Subspace Projection Method for Time-Domain PPV Computation
Research Manuscript Accshield: Operator-Aware Robust Scheduling for Fault-Tolerant AI Accelerators
Research Manuscript FBS: Accelerating CNN Inference over RNS-CKKS with Fewer Bootstrapping Sparsity
Research Manuscript Throughput-Oriented Speculative Decoding via Intra-Device Parallelism
Research Manuscript Crystal-KV: Efficient KV Cache Management for Chain-of-Thought LLMs via Answer-First Principle
Research Manuscript Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
Research Manuscript SpArC: Sparse Tensor Accelerator Compilation with Scheduling and Mapping
Research Manuscript HyPAS: A Hybrid Optimization Framework for Placement and Sizing Co-Optimization
Late Breaking Results Late Breaking Results: QUBO Approaches to Logic Equivalence Checking and Testing
Engineering Presentation Hunting RTL Glitches Before They Burn Power: A Practical RTL Success Story
Research Manuscript WSC-Cost: An Accurate Cost Modeling Framework for Wafer-Scale Chips
Engineering Poster A Scalable Timing Analysis and Closure Methodology for Ultra-Large Designs
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
Research Manuscript iPCL-M: Pre-Training of Chip Layout for Metrics Evaluation and Optimization
Research Manuscript RM Poster Session Eight
DAC Pavilion Panel From RTL to Reality: Building Security into the Silicon Lifecycle
Engineering Presentation Deep Reinforcement Learning Paradigm for Analog Design Automation
Research Manuscript Shared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen Synthesis
Research Manuscript Unlocking Automated Datapath Gating via Machine Learning Power Prediction
Research Manuscript PRISM: Dynamic Primitive-Based Forecasting for Large-Scale GPU Cluster Workloads
Engineering Presentation A Service-Aware Energy-Efficient DVFS Framework for System-on-Chip Architectures
Research Manuscript Shared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen Synthesis
Research Manuscript Unlocking Automated Datapath Gating via Machine Learning Power Prediction
Engineering Presentation A Service-Aware Energy-Efficient DVFS Framework for System-on-Chip Architectures
Engineering Presentation No More Blind Spots: RTL Modeling of Metastability for CDC Verification
Engineering Poster Advanced Automation for DC Die Generation and Verification
Engineering Poster Advanced Hard IP Integration Requirement Extraction and Checker
Engineering Presentation Advanced Hard IP Integration Requirement Extraction and Checker
Work in Progress Lockroute: A Spatial Locking Framework for Parallel Global Routing
Research Manuscript Parallel Combinational Equivalence Checking Through Factored Form Sharing
Research Manuscript Path-Based Timing Analysis Acceleration via Segment-Level Timing Arc Reuse
Research Manuscript Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
Research Manuscript DCTS: Differentiable Clock Tree Synthesis Based on Probabilistic Graphical Model
Engineering Poster Gladiator 3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration
Research Manuscript CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
Additional Meeting Si2 Openaccess Forum
DAC Pavilion Panel Build vs Buy: Who Owns the Intelligence Behind Tomorrow's Chips?
Research Manuscript Decoding the Past: Recovering Sensitive Data from SRAM Aging Imprints
Engineering Presentation Hardening Security of HW IPs by Verifying Their Negative Space Formally
Research Manuscript Foundations and Frontiers: Bridging Traditional EDA and Generative AI
Research Manuscript Computing Without Waste: Lean and Scalable Neural Architectures
Research Manuscript RM Poster Session Two
Research Manuscript Sparsity- and Tolerance-Aware Temporally Redundant Neural Networks
Research Manuscript Enabling AI ASICs for Zero Knowledge Proof
Late Breaking Results Late Breaking Results: 3D Analytical Placement with Smoothed Multi-Die Wirelength Model
Research Manuscript RM Poster Session One
Research Manuscript Test Point Insertion with ATPG-Free Self-Supervised Learning
Research Manuscript Scalable Reliability Assessment of DNNs Through Simultaneous Fault Injection
Research Manuscript LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout
Research Manuscript Stateful Embedded Fuzzing Using Peripheral-Accurate Systemc Virtual Prototypes
Research Manuscript RM Poster Session One
Engineering Poster Hierarchical Cost-Efficient IR Methodology for AI SoCs
Late Breaking Results Late Breaking Results: QUBO Approaches to Logic Equivalence Checking and Testing
Research Manuscript HyPAS: A Hybrid Optimization Framework for Placement and Sizing Co-Optimization
Research Manuscript RM Poster Session Six
Research Manuscript Revolutionizing Synthesis Flows
Research Manuscript Shortcircuit: Alphazero-Driven Generative Circuit Design
Late Breaking Results Late Breaking Results: "describing" Your Way to a Functional Microfluidic Chip
Work in Progress Late Breaking Results: A Scalable and Efficient Multi-Layer 3D-Printed Microfluidic Design Synthesis
Taiwan
Research Manuscript Predictable Precision: Resilience and Timing in the Era of AI
Research Manuscript RM Poster Session Seven
Research Manuscript Advancing Macro Placement: Integrating Proven Design Practices with Reinforcement Learning
Research Manuscript Silicon Whisperers: When LLMs Learn to Speak RTL
Work in Progress STA Accuracy Validation: A Machine Learning Approach
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Research Manuscript RM Poster Session Four
Work in Progress SPICEMixer - Netlist-Level Circuit Evolution
Work in Progress SNN Accelerator Testing via Sparse Test Matrices
Engineering Presentation Accelerating X-State Aware Power Simulation Using Advanced Hardware Emulation
Engineering Presentation Shifting System-Level Verification Left with Firmware-Driven Execution
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Engineering Poster TAWT: Towards Autonomous Wrapper Tuning
Work in Progress Compact ML-Based Glitch Propagation Modeling of Standard Cells
Engineering Poster ARTEMIS: Agentic AI for EDA
Engineering Poster Accurate Characterization Methodology for Combo-IO Design with Concurrent Switching Outputs for Precise Power Analysis at SoC
Engineering Poster Identifying Weakest Links: A Cell Scoring Metric for Robust Design in Advanced Nodes
Engineering Poster Liberty-Based Profiling for IP Benchmarking
Research Manuscript Athena: Analytical Timing-Aware Pre-Silicon Estimation of Side-Channel Leakage
Engineering Poster A Simple and Predictable Solution for Early Full-Chip LVS Convergence
Engineering Poster FPGA-to-ASIC Conversion via Hierarchical Wrapping
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
Engineering Special Session Advancements in Emulation and Prototyping for Semiconductor: Hardware Tools, Challenges, and FPGA Solutions
Engineering Poster Bridging Hardware-Software Abstraction In UVM Verification
Engineering Presentation Pre-Silicon Hardware Security: Side-Channels and Edge AI
Engineering Presentation AI-Enabled EDA Cloud Infrastructure and Design Optimization for Next-Generation Semiconductor Design
Engineering Poster Gladiator Sigma Profiling: Profiling Solution for Power Integrity Signoff
DAC Pavilion Panel Agentic AI in EDA: Who's in Control?
Work in Progress SPICEMixer - Netlist-Level Circuit Evolution
Engineering Poster Mixed Transistor Design Closure
Research Manuscript ARC-SRAM: A Memory Subarray with Local Addressing and Reduced Access Energy
Research Manuscript Athena: Analytical Timing-Aware Pre-Silicon Estimation of Side-Channel Leakage
Analyst Presentation A View from Wall Street
Engineering Poster Gladiator A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs
Engineering Presentation A Service-Aware Energy-Efficient DVFS Framework for System-on-Chip Architectures
Research Manuscript Shared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen Synthesis
Research Manuscript Unlocking Automated Datapath Gating via Machine Learning Power Prediction
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Engineering Poster Gladiator Multi Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN Model
United States of America
Engineering Poster New Thermal Analysis Workflow for 3DIC Designs
Research Manuscript Faster-MoA: Low-Latency Tree-Structured MoA Serving with Early Exit and Agent-Aware Prefill-Decode Overlap
Research Manuscript RM Poster Session Seven
Research Manuscript Rethinking AI Compute: Cross-Layer Co-Design Beyond Conventional GPUs
Engineering Presentation A Mixed-Domain Modeling Approach for Hatched Ground Planes in 3D Chiplet Die-to-Die Interconnect
Research Manuscript Silicon Integrity 2.0: Detection, Tracking, and Attestation
Research Manuscript HyPAS: A Hybrid Optimization Framework for Placement and Sizing Co-Optimization
Research Manuscript Crystal-KV: Efficient KV Cache Management for Chain-of-Thought LLMs via Answer-First Principle
Late Breaking Results Late Breaking Results: Astfusion -- Two-Stage Structural Enhancement Learning for Robust HLS Code Generation
Late Breaking Results Late Breaking Results: Efficient MoE-ViT Gating on Edge Accelerator via Dynamic Expert Routing and Quantized Router
Research Manuscript RM Poster Session Five
Research Manuscript Where Biology Meets Computation: Next‑Gen Bio‑Cyber‑Physical Innovations
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
Research Manuscript Accshield: Operator-Aware Robust Scheduling for Fault-Tolerant AI Accelerators
Research Manuscript HyPAS: A Hybrid Optimization Framework for Placement and Sizing Co-Optimization
Late Breaking Results Late Breaking Results: QUBO Approaches to Logic Equivalence Checking and Testing
China
Research Manuscript PMU-Faker: The Apparently Harmless Performance Monitoring Unit Events Are Actually Harmful
Research Manuscript Seeing the Unseen: Reverse Engineering Hidden PMU Events by Differential Analysis and Simulation Validation
Research Manuscript Unveiling the Security Risks Driven by the Hardware Interrupts
Engineering Poster Gladiator 3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration
China
Research Manuscript COLA: Enabling Low-Latency Reads for Flash-Based SSDs via Code Length Adaptation
Research Manuscript Emudrop: A Minimalistic, Hardware-Based Emulation Detection Approach Through Intel Reserved Opcodes
Research Manuscript Instruction-Level Side-Channel Disassembly on Modern Complex CPUs via Voltage Waveform Analysis
Research Manuscript Mistletunnel: Attacking KASLR on Apple M-Series Silicon with a Novel TLB Side Channel
Research Manuscript PMU-Faker: The Apparently Harmless Performance Monitoring Unit Events Are Actually Harmful
Research Manuscript Seeing the Unseen: Reverse Engineering Hidden PMU Events by Differential Analysis and Simulation Validation
Research Manuscript Thrend: Mitigating Counting Thread-Based Fine-Grained Timing on Arm and Apple CPUs
Research Manuscript Unveiling the Security Risks Driven by the Hardware Interrupts
Research Manuscript GenDSE: Generative CPU Design Space Exploration via Sequential Decision Making
Research Manuscript Quantum Circuit Synthesis Using an Exact T Library
Research Manuscript TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
Research Manuscript Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging
Research Manuscript Strix: Re-Thinking NPU Reliability from a System Perspective
Research Manuscript AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning
Research Manuscript Targeted Bit-Flip Attacks on LLM-Based Agents
Research Manuscript Pillarsparse: Rethinking Unstructured Sparse Formats for Tensor Cores
Research Manuscript AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning
Research Manuscript DRCGen: A Controllable DRC Violation Case Generator with Cross-PDK Transferability for Rule-Deck and Tool Validation
Research Manuscript Duet: Exploiting High-Order Lossless Sparsity for Bit-Serial Transformer Acceleration via Distribution-Aware Pruning
Research Manuscript Is 2D Gaussian Enough? A Sort-Free 3D Gaussian Splatting Inference Architecture with Geometry Guidance
Research Manuscript STAC: Spatial-Temporal Activation Contextualization for Resilient LLM Inference
Research Manuscript Dataflowgen: An MLIR-Based Compiler for Efficient Dataflow Accelerator Generation
Research Manuscript Dynamic-Cost Area Recovery for Fracturable LUT-Based FPGAs
Research Manuscript Alphaplacer: Analog Placement Enhanced by Monte Carlo Tree Search
Research Manuscript Diffsp: Differentiable Sequence Pair-Based Analog Placement
Research Manuscript STAC: Spatial-Temporal Activation Contextualization for Resilient LLM Inference
Research Manuscript Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
Research Manuscript KL-MoE: A Hierarchical MoE Pruning Framework Exploiting KL Divergence
Engineering Presentation Physical Signoff at Scale: Tackling TSV, Interposer, and ESD in 3DIC Systems
Research Manuscript Ciphershield: Safeguarding DNN Inputs from Ciphertext Side-Channels in TEE
Research Manuscript Harnessing the Noise: p-Bits, ZKPs, and Resilient AI
Research Manuscript Accshield: Operator-Aware Robust Scheduling for Fault-Tolerant AI Accelerators
Research Manuscript An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference
Research Manuscript Celle: Automated Standard Cell Library Extension via Equality Saturation
Research Manuscript DRIFT: Harnessing Inherent Fault Tolerance for Efficient and Reliable Diffusion Model Inference
Research Manuscript GPU-Fuzz: Finding Memory Errors in Deep Learning Frameworks
Research Manuscript Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge
Research Manuscript CHiRM-DSE: CodeLLM-Based Hierarchical and Rule-Mining Guided DSE for FPGA Accelerators
Research Manuscript Crystal-KV: Efficient KV Cache Management for Chain-of-Thought LLMs via Answer-First Principle
Research Manuscript Efficient HLS Accelerator Floorplan on Multi-Die FPGA Aided by Graph Neural Networks
Research Manuscript Idealsim: Efficient Ideal Scenario Modeling for Processor Upper-Bound Performance Analysis
Late Breaking Results Late Breaking Results: Efficient MoE-ViT Gating on Edge Accelerator via Dynamic Expert Routing and Quantized Router
Late Breaking Results Late Breaking Results: HUSH: Silencing Inter-Core Interference in Real-Time Cache Analysis
Research Manuscript Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
Research Manuscript SpArC: Sparse Tensor Accelerator Compilation with Scheduling and Mapping
Research Manuscript Etherssd: An In-Storage Ethereum Analytics Platform with Minimized I/O and Authentication Overhead
Research Manuscript PIMGRAG: A Heterogeneous PIM Architecture for Graph-Based Retrieval-Augmented Generation
Research Manuscript SpecANNS: Accelerating Graph-Based Approximate Nearest Neighbor Search with Speculative In-Storage Computing
Research Manuscript TierANNS: Scalable Graph-Based ANNS with CXL-Enabled Tiered Data Placement
Research Manuscript Akirarust: Re-Thinking LLM-Aided Rust Repair Using a Feedback-Guided Thinking Switch
Research Manuscript From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
Research Manuscript Strix: Re-Thinking NPU Reliability from a System Perspective
Engineering Poster Accelerating IR and Timing Convergence with Revolutionary IR-ECO
Research Manuscript Per Flow Asynchronous Traffic Shaping in Time Sensitive Networking
Research Manuscript Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
Research Manuscript ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
Research Manuscript Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
Research Manuscript Circuitdiff: Bridging Netlist Knowledge with RTL Based on Graph Denoising Diffusion
Research Manuscript Insights from Verification: Training a Verilog Generation LLM Using Reinforcement Learning with Testbench Feedback
Late Breaking Results Late Breaking Results: LLM-Driven Constraint Generation and Deferred Shape Exploration for Analog IC Floorplanning
Research Manuscript Paretopilot: Global Optimization Reasoning on HLS Design Space Exploration with LLMs
Research Manuscript Toward True-3D Timing-Driven Analytical Global Placement for Mixed-Size Face-to-Face 3D ICs
Research Manuscript RM Poster Session Three
Research Manuscript Securing the Stack: Embedded and Cross-Layer Defenses from Silicon to Systems
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Research Manuscript Amoeba: Runtime Tensor Parallel Transformation for LLM Inference Services
Research Manuscript Lhgstore: An In-Memory Learned Graph Storage for Fast Updates and Analytics
Research Manuscript Pipegs: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning
Research Manuscript SpRDA: An Efficient Sparse Accelerator for Robotics Diffusion Model
Research Manuscript Agent-Per-Qubit: Automated Qubit Placement for Fault-Tolerant Quantum Computing
Research Manuscript Pillarsparse: Rethinking Unstructured Sparse Formats for Tensor Cores
Research Manuscript Accelerating AI+SAR Applications Through Enhanced Graph Optimization
Research Manuscript Etherssd: An In-Storage Ethereum Analytics Platform with Minimized I/O and Authentication Overhead
Research Manuscript Freebit: Unleashing the Performance Potential of Low-Bit LLMs Through PIM
Research Manuscript PIMGRAG: A Heterogeneous PIM Architecture for Graph-Based Retrieval-Augmented Generation
Research Manuscript GRACE: A Ground Plane Generation and Re-Routing Aware Co-Design Engine
China
Research Manuscript Strix: Re-Thinking NPU Reliability from a System Perspective
Research Manuscript Onyx: Efficient Transaction Processing with Real Processing-in-Memory Prototypes
Research Manuscript TRIDENT: An End-to-End Streaming Accelerator for TriSpGEMM
Research Manuscript Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
Research Manuscript Celle: Automated Standard Cell Library Extension via Equality Saturation
Research Manuscript Intelligent Systems for Physical & Structured Worlds
Research Manuscript RM Poster Session Nine
Research Manuscript ATOM-3D: Analytical Three-Dimensional Orientation-Aware Mixed-Size Placer
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Research Manuscript CPA-BNN: A Secure and Efficient CIM and PUF Architecture for BNN Accelerator
Research Manuscript Pipegs: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning
Research Manuscript SpRDA: An Efficient Sparse Accelerator for Robotics Diffusion Model
Engineering Poster Pss–enabled Design Space Exploration for Energy Management Systems
Research Manuscript Architecting the Future: Cross-Layer Breakthroughs in Compute and Memory
Research Manuscript RM Poster Session Three
Research Manuscript TDH-GNN: An Efficient Topology-Driven Accelerator for Dynamic Heterogeneous GNN
Research Manuscript Pillarsparse: Rethinking Unstructured Sparse Formats for Tensor Cores
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Engineering Presentation Using Arm Native Acceleration with VLAB Virtual Platforms
Research Manuscript Hierarchical Boundary Recovery: Overcoming Synthesis Obscurity via SAT Sweeping
Engineering Poster Automotive Logic Test Power Management
Research Manuscript Knowledge-Driven Hybrid SSD Management Enhanced by Fine-Tuned LLMs
Research Manuscript From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
Research Manuscript Strix: Re-Thinking NPU Reliability from a System Perspective
Research Manuscript WSC-Cost: An Accurate Cost Modeling Framework for Wafer-Scale Chips
Engineering Poster Enabling Time-Aware Systems Across Silicon-System Boundary
Research Manuscript Accshield: Operator-Aware Robust Scheduling for Fault-Tolerant AI Accelerators
Research Manuscript FBS: Accelerating CNN Inference over RNS-CKKS with Fewer Bootstrapping Sparsity
Research Manuscript TRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI
Research Manuscript An Efficient Heterogeneous Co-Design for Fine-Tuning on a Single GPU
Research Manuscript Deinfer: Efficient Parallel Inferencing for Decomposed Large Language Models
Engineering Presentation Scalable Verification Methodology for Stacked 3D Chiplet-Based Designs Using SIP Flow
Research Manuscript Exploiting Movable Logical Qubits for Lattice Surgery Compilation
Work in Progress Late Breaking Results: Guiding Compiler Optimizations for Neutral Atom Quantum Computers Through Visualizations
Research Manuscript Minimizing the Number of Code Switching Operations in Fault-Tolerant Quantum Circuits
Research Manuscript Search Smarter, Not Harder: A Scalable, High-Quality Zoned Neutral Atom Compiler
Engineering Poster Design Verification Automation (DVA) for PCB Signal and Power Integrity
Research Manuscript Scaling Intelligence for the Physical World
Research Manuscript DR. OPC: Differentiable Rasterization for Advanced Optical Proximity Correction
Engineering Presentation Adaptive QoS Optimization for SoC Performance Enhancement Using Dueling Double Deep Q-Networks
Engineering Poster Unifying Pre- and Post-Silicon Software Validation Through Modeling
Research Special Session Toward Agentic Solutions for DRC Challenges in Digital VLSI Design
Research Manuscript Legotherm: Modular and Reusable Thermal Model for Chiplet-Based Heterogeneous Integration
Research Manuscript Mixed-Structure Double-Sided Redistribution Layer Routing for Glass Interposer-Based 5.5D ICs
Research Manuscript WFH-BFs: Dynamic Defense Against DNN Bit-Flips via a Weight Function Hierarchy
Research Manuscript WSC-Cost: An Accurate Cost Modeling Framework for Wafer-Scale Chips
Research Manuscript Slcross: Cross-Component System-Level Cache Side-Channel Attacks on Apple M2 SoC
China
Research Manuscript Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells
Research Manuscript Cell-Structure-Independent Transistor-Level Placement and MOL-Aware Routing Framework Beyond the Standard-Cell Paradigm
Late Breaking Results Late Breaking Results: A Coarse-to-Fine PCB Placement Framework via LLM-Guided Component Grouping and Group-Aware Placement
Late Breaking Results Late Breaking Results: A Fully Differentiable Rectilinear Minimum Spanning Tree Wirelength Model for Global Placement
Late Breaking Results Late Breaking Results: Merge-Aware Placement and DP-Based Wave Propagation Routing for Scalable Flip-FET Cell Layout Synthesis
Late Breaking Results Late Breaking Results: Physics-Aware Diffusion Framework for Transistor-Level Placement Beyond Standard-Cell Boundary
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Research Manuscript Nash: A Neighbor-Aware Shared Memory Design on GPU for Accelerating AI Workloads
Research Manuscript GenDSE: Generative CPU Design Space Exploration via Sequential Decision Making
Late Breaking Results Neural Subgraph Matching for Hardware Decompilation in Gate-Level Netlists
Engineering Presentation Lint-Free: A Generative AI Approach to Large Scale Autonomous RTL-Lint Correction
Research Manuscript Cupilot: A Strategy-Coordinated Multi-Agent Framework for CUDA Kernel Evolution
Research Manuscript Freebit: Unleashing the Performance Potential of Low-Bit LLMs Through PIM
Research Manuscript Edgesc: Universal Stochastic Computing Architecture for Efficient Edge Detection
Research Manuscript GRACE: A Ground Plane Generation and Re-Routing Aware Co-Design Engine
Research Manuscript Expcheck: Dynamic Expert-Aware Checkpointing for Mixture-of-Experts Based Models
Research Manuscript Per Flow Asynchronous Traffic Shaping in Time Sensitive Networking
Research Manuscript PRISM: Dynamic Primitive-Based Forecasting for Large-Scale GPU Cluster Workloads
Research Manuscript Quantum Circuit Synthesis Using an Exact T Library
Research Manuscript Can Asymmetric Tile Buffering Be Beneficial?
Engineering Presentation AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
Research Manuscript Slcross: Cross-Component System-Level Cache Side-Channel Attacks on Apple M2 SoC
Research Manuscript Dart: Towards Redundancy-Free RTL Simulation via DAG-Driven Execution
Research Manuscript Gwrite: Offloading Replication in Disaggregated Memory Systems
Research Manuscript SSD Reforge: Dynamic Parity Management to Extend SSD Lifetime Under Aging
Research Manuscript Targeted Bit-Flip Attacks on LLM-Based Agents
Research Manuscript PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
X
Research Manuscript GEMIR: Graph-Based Joint Modeling of Electromigration and IR Drop for Power Grid
Late Breaking Results Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond
Research Manuscript Parallelizing Complementary Approximate Reachability
Engineering Presentation Hunting RTL Glitches Before They Burn Power: A Practical RTL Success Story
Research Manuscript Runtime-ADAR: Runtime Anomaly Detection and Attack Recovery in Encrypted DNNs
Research Manuscript WFH-BFs: Dynamic Defense Against DNN Bit-Flips via a Weight Function Hierarchy
Research Manuscript ATOM-3D: Analytical Three-Dimensional Orientation-Aware Mixed-Size Placer
Research Manuscript DRΛMA: Detailed Routing by a Versatile Maze Routing Algorithm
Research Manuscript GRACE: A Ground Plane Generation and Re-Routing Aware Co-Design Engine
Late Breaking Results Late Breaking Results: A High-Performance TFHE Bootstrapping Accelerator with Heterogeneous Processing Engines
Research Manuscript RM Poster Session Four
Research Manuscript Flowplace: Flow Matching for Chip Placement
Research Manuscript How Can Reinforcement Learning Achieve Expert-Level Placement?
Research Manuscript COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging
Research Manuscript Compart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning
Research Manuscript FSGen: Agile Fused and Sparse Accelerator Generator with Accurate Power Model for LLM Applications
Research Manuscript G-Power: Architecture-Level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs
Research Manuscript Impart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning
Research Manuscript LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power
Research Special Session LLMs for Silicon: From Code Generation to Autonomous EDA and Layout Closure
Research Manuscript RTL-Benchmt: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
Research Manuscript RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-Based Paradigm
Research Manuscript Shortcircuit: Alphazero-Driven Generative Circuit Design
Research Manuscript Graph-Based Attack-Chain Traceback Across Multiple In-Vehicle Network Domains
Research Manuscript Pillarsparse: Rethinking Unstructured Sparse Formats for Tensor Cores
Research Manuscript Breaking the Tuning Barrier: Zero-Hyperparameters Yield Multi-Corner Analysis Via Learned Priors
Research Manuscript Exploiting Function-Family Structure in Analog Circuit Optimization
Research Manuscript From Fluid Dynamics to Chip Design: PDE Foundation Model Address Data Bottleneck in 3D-ICs Thermal Simulation
Research Manuscript IGNITE: An Inquisitive and Graph-Aware Neural Circuit Simulator with Two-Stage Enhanced In-Context Learning
Research Manuscript Legotherm: Modular and Reusable Thermal Model for Chiplet-Based Heterogeneous Integration
Research Manuscript OpenACMv2: An Accuracy-Constrained Co-Optimization Framework for Approximate DCiM
Research Manuscript PIANO: Physics-Informed Admittance Neural Operator for Fast Power Integrity Analysis
Research Manuscript Powerpath: Internal-Probe-Free Search Interval Reduction for Efficient Statistical Sequential Constraint Characterization
Research Manuscript RM Poster Session Five
Research Manuscript RM Poster Session Two
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Engineering Poster Enabling Time-Aware Systems Across Silicon-System Boundary
Research Manuscript Dart: Towards Redundancy-Free RTL Simulation via DAG-Driven Execution
Research Manuscript Expcheck: Dynamic Expert-Aware Checkpointing for Mixture-of-Experts Based Models
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript iPCL-M: Pre-Training of Chip Layout for Metrics Evaluation and Optimization
Research Manuscript Alphaplacer: Analog Placement Enhanced by Monte Carlo Tree Search
Research Manuscript Diffsp: Differentiable Sequence Pair-Based Analog Placement
Research Manuscript Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits
Research Manuscript Mappingevolve: LLM-Driven Code Evolution for Technology Mapping
Research Manuscript Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
Research Manuscript TRACE: Learning to Compute on Circuit Graphs
Research Manuscript An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference
Research Manuscript Flowplace: Flow Matching for Chip Placement
Research Manuscript How Can Reinforcement Learning Achieve Expert-Level Placement?
Research Manuscript How Can Reinforcement Learning Achieve Expert-Level Placement?
Engineering Presentation AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
Research Manuscript Floquet-Based Subspace Projection Method for Time-Domain PPV Computation
Research Manuscript Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
Engineering Poster Design-for-FV Approach on a RISC-V Memory Page Walker
Research Manuscript HW-Router: Hardware-Aware Routing for Scalable Multi-LLM Serving
Research Manuscript Flowplace: Flow Matching for Chip Placement
Research Manuscript How Can Reinforcement Learning Achieve Expert-Level Placement?
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Research Manuscript Targeted Bit-Flip Attacks on LLM-Based Agents
Engineering Poster AI-Enabled Flow for Silicon Area Reduction and Design Closure
Engineering Poster ECO Strategy for BIG DIE SOC Convergence
Engineering Poster Ai&cell Based Analog Circuit Topology Generator(ctgen)
Engineering Presentation Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
Engineering Presentation Using ML-Assisted Side-Channel Analysis in Simulation: A Case Study on AES-GCM
Research Manuscript NVLLM: A 3D NAND-Centric Architecture Enabling Edge on-Device LLM Inference
Research Manuscript GenDSE: Generative CPU Design Space Exploration via Sequential Decision Making
Research Manuscript Towards Practical Live Migration for Heterogeneous Confidential Virtual Machines
Research Manuscript DRCA: Reliable Bitwise Logic in DRAM via Dual-Rail Compute and Access
Research Manuscript Floquet-Based Subspace Projection Method for Time-Domain PPV Computation
Research Manuscript NVLLM: A 3D NAND-Centric Architecture Enabling Edge on-Device LLM Inference
Engineering Presentation AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization
Late Breaking Results Late Breaking Results: Power Mesh Construction for 3D-IC with Backside Power Delivery
DAC Pavilion Panel Agentic AI in EDA: Who's in Control?
Research Manuscript Optimizing Dynamic-Shape Neural Networks: A Unified Approach to Adaptive Tuning
Research Manuscript Making Sense of Job Preemption for Distributed Deep Learning Acceleration
Research Manuscript Differentiable Dreams: GPU-Powered Litho Gets Its Gradient Groove Back
Research Manuscript Pushing the Limits of Inverse Lithography with Generative Reinforcement Learning
Research Manuscript RM Poster Session Five
Research Special Session Toward Agentic Solutions for DRC Challenges in Digital VLSI Design
Late Breaking Results Late Breaking Results: QUBO Approaches to Logic Equivalence Checking and Testing
Research Manuscript CAPA: Convertibility-Aware Mixed-Precision Accelerator for Asymmetric GEMM in Weight-Only Quantized LLMs
Research Manuscript CLUE-ECC: Low-Cost LPDDR6 Reliability Enhancement by Integrating System ECC with On-Die ECC
Research Manuscript Test Point Insertion with ATPG-Free Self-Supervised Learning
Research Manuscript Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
Research Manuscript HYPER-CIM: Hierarchical Predictive Exploration and Realizable Design Flow for High-Efficient Digital CIM
Late Breaking Results Late Breaking Results: Physics-Aware Diffusion Framework for Transistor-Level Placement Beyond Standard-Cell Boundary
Research Manuscript Cupilot: A Strategy-Coordinated Multi-Agent Framework for CUDA Kernel Evolution
Engineering Poster Xchip: A Guardrailed Agentic Gen-AI Front-End Flow from Intent to GDSII
Research Manuscript Advancing the Frontier of Neuromorphic Learning Systems
Research Manuscript RM Poster Session Two
Research Manuscript Memory-Busting Inference Engines
Research Manuscript Analytically-Derived Hybrid Net–pin Weighting for Timing-Driven Global Placement
Research Manuscript Dropping Multiple Literals per SAT Call in IC3 Model Checking
Research Manuscript An Efficient Heterogeneous Co-Design for Fine-Tuning on a Single GPU
Research Manuscript An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference
Research Manuscript Memory-Busting Inference Engines
Research Manuscript RM Poster Session Five
Research Manuscript RM Poster Session Four
China
Engineering Presentation Enabling PSS-Driven Early SoC Verification By Enriching IP-XACT Information
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Engineering Poster Multi-Cycle Dynamic Vectorless Analysis for Improved PDN Signoff
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
Research Manuscript Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
China
Research Manuscript Chimera: A Unified FHE Accelerator with Enhanced Compatibility for TFHE
Research Manuscript STAC: Spatial-Temporal Activation Contextualization for Resilient LLM Inference
Research Manuscript GenDSE: Generative CPU Design Space Exploration via Sequential Decision Making
Research Manuscript UniNL: Unifying Fragmented Non-Linear Operators for Efficient Edge LLM Inference
Research Manuscript Crosstalk Timing Prediction via Graph Prompt Learning in Aggressor-Victim RC Networks
Research Manuscript Diffsp: Differentiable Sequence Pair-Based Analog Placement
Research Manuscript GEMIR: Graph-Based Joint Modeling of Electromigration and IR Drop for Power Grid
Research Manuscript HyPAS: A Hybrid Optimization Framework for Placement and Sizing Co-Optimization
Research Manuscript LLM4SDC: Leveraging Multi-Agent System for Automated SDC Generation and Benchmarking
Research Manuscript Path-Based Timing Analysis Acceleration via Segment-Level Timing Arc Reuse
Research Manuscript TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
Late Breaking Results Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond
Research Manuscript Semi-Virtual Addressing to Enhance Memory Safety on Microcontrollers
Engineering Presentation Architectural Formal Verification of Configurable Address Translation Logic for Early Bug Exposers
Engineering Poster Low Power Optimization Through Fast and Accurate Time-Based Power Analysis
Research Manuscript TOPCELL: Topology Optimization of Standard Cell via LLMs
Research Manuscript AMBER: A Unified Accelerator for Multi-Precision LLM Inference Exploiting Bit-Level Redundancy and Reconfigurability
Research Manuscript Hiband: A Hierarchical Bandwidth-Aware HB-DRAM Accelerator with Array-Level Co-Execution and Reconfigurable NoC for LLM Inference
Research Manuscript WSC-Cost: An Accurate Cost Modeling Framework for Wafer-Scale Chips
Research Manuscript Coordinated Clip-Wise Gradient Scheduling for Full-Chip ILT via Policy Learning
Research Manuscript Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
Research Manuscript The Edge-Lord Chronicles: Tiny Gestures, Big LLMs, and Cluster Chaos
Research Manuscript Runtime-ADAR: Runtime Anomaly Detection and Attack Recovery in Encrypted DNNs
Research Manuscript WFH-BFs: Dynamic Defense Against DNN Bit-Flips via a Weight Function Hierarchy
Research Manuscript Fast Template Matching for Quantum Circuits Using Hypergraph
Research Manuscript Fast Template Matching for Quantum Circuits Using Hypergraph
Engineering Presentation A Unified QA Framework for Intel Library Validation Using Siemens Solido Crosscheck
Research Manuscript Making Sense of Job Preemption for Distributed Deep Learning Acceleration
Research Special Session Quantum and AI Convergence
Research Manuscript MASQ: Accelerating Masked Diffusion via Stage-Wise Multi-Precision Quantization
Work in Progress Accelerating Functional Fault Grading for Flash and DRAM Designs
Research Manuscript MXP: A Posit-Inspired Microscaling Format for Vision-Language Tasks
Work in Progress Accelerating Functional Fault Grading for Flash and DRAM Designs
Research Manuscript Flip-FET-Based VLSI Design Framework with Congestion-Aware Dual-Side Routing
Research Manuscript Computing Without Waste: Lean and Scalable Neural Architectures
Research Manuscript RM Poster Session Two
Research Manuscript Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging
Research Manuscript Strix: Re-Thinking NPU Reliability from a System Perspective
Research Manuscript Tdsnap: Enabling Secure Function-as-a-Service with Trusted Domain Snapshots
Research Manuscript ATOM-3D: Analytical Three-Dimensional Orientation-Aware Mixed-Size Placer
Research Manuscript DRΛMA: Detailed Routing by a Versatile Maze Routing Algorithm
Research Manuscript RM Poster Session Five
Research Manuscript Escaping Flatland: A Placement Flow for Enabling 3D FPGAs
Research Manuscript BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs
Research Manuscript CPW-SMO: Generating Mask Sets and Common Source for Maximum Common Process Window
Research Manuscript Coordinated Clip-Wise Gradient Scheduling for Full-Chip ILT via Policy Learning
Research Manuscript DR. OPC: Differentiable Rasterization for Advanced Optical Proximity Correction
Research Manuscript Diffsp: Differentiable Sequence Pair-Based Analog Placement
Research Manuscript Flexicts: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs
Research Manuscript HyPAS: A Hybrid Optimization Framework for Placement and Sizing Co-Optimization
Research Manuscript Integrated Timing-Driven Placement for Hybrid-Bonding-Based Face-to-Face 3D ICs
Research Manuscript Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC
Research Manuscript Schemacoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting
Research Manuscript TOPCELL: Topology Optimization of Standard Cell via LLMs
Research Manuscript Knowledge-Driven Hybrid SSD Management Enhanced by Fine-Tuned LLMs
Research Manuscript Fast Template Matching for Quantum Circuits Using Hypergraph
Research Manuscript Quantum Circuit Synthesis Using an Exact T Library
Research Manuscript TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
Research Manuscript RM Poster Session Two
Research Manuscript PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
Research Manuscript Orchestrating LLM Systems at Scale: Heterogeneity, Memory, and Throughput
Research Manuscript CPW-SMO: Generating Mask Sets and Common Source for Maximum Common Process Window
Research Manuscript Coordinated Clip-Wise Gradient Scheduling for Full-Chip ILT via Policy Learning
Research Manuscript PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
Research Manuscript Flowplace: Flow Matching for Chip Placement
Research Manuscript How Can Reinforcement Learning Achieve Expert-Level Placement?
Research Manuscript Shortcircuit: Alphazero-Driven Generative Circuit Design
Research Manuscript Accshield: Operator-Aware Robust Scheduling for Fault-Tolerant AI Accelerators
Engineering Presentation A Rule-Aware Layout Conversion Framework for Back-End Physical Design
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Engineering Presentation Advancing Silicon Lifecycle Management with Embedded Trace
DAC Pavilion Panel What Are VCs Looking for at DAC?
Engineering Special Session From Bit to Qubit: EDA Meets Quantum
DAC Pavilion Panel What Are VCs Looking for at DAC?
Research Manuscript RM Poster Session Four
Research Manuscript Greenllm: SLO-Aware Dynamic Frequency Scaling for Energy-Efficient LLM Serving
Research Manuscript SSD Reforge: Dynamic Parity Management to Extend SSD Lifetime Under Aging
Research Manuscript Chiplanner: Physically-Aware and Timing-Driven Design Planner for 2.5D Multi-Chiplet Systems
Research Manuscript Compilation Tells Energy: Rethinking Power Modeling for DNN Accelerator Agile Design
Research Manuscript GEMIR: Graph-Based Joint Modeling of Electromigration and IR Drop for Power Grid
Late Breaking Results Late Breaking Results: HUSH: Silencing Inter-Core Interference in Real-Time Cache Analysis
Research Manuscript Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
Research Manuscript G-Power: Architecture-Level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs
Research Manuscript Pipegs: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning
Research Manuscript SpRDA: An Efficient Sparse Accelerator for Robotics Diffusion Model
Research Manuscript OpenSUN: An Open Platform for Exploring Scale-Up Network Systems
Research Manuscript CODA: A Computation-Data Decoupled Dataflow Paradigm for DNN Computing on NPUs
Research Manuscript PRS: An Efficient Parallel SAT Framework
Research Manuscript Parallel Combinational Equivalence Checking via Sweeping-Based Task Scheduling
Research Manuscript GPU-Fuzz: Finding Memory Errors in Deep Learning Frameworks
Research Manuscript RM Poster Session Three
Research Manuscript Securing the Stack: Embedded and Cross-Layer Defenses from Silicon to Systems
Research Manuscript DCTS: Differentiable Clock Tree Synthesis Based on Probabilistic Graphical Model
Research Manuscript Epicell: Electro-Physical Co-Modeling for Standard Cell PPA Prediction
Research Manuscript PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
Research Manuscript Legend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
Research Manuscript Nash: A Neighbor-Aware Shared Memory Design on GPU for Accelerating AI Workloads
Research Manuscript From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
Research Manuscript Strix: Re-Thinking NPU Reliability from a System Perspective
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Research Manuscript PIMA-SecDB: Processing-in-Memory Acceleration for Fully Homomorphic Encryption Databases
Research Manuscript RM Poster Session Six
Research Manuscript RM Poster Session Eight
Research Manuscript Towards Practical Live Migration for Heterogeneous Confidential Virtual Machines
Research Manuscript Celle: Automated Standard Cell Library Extension via Equality Saturation
Research Manuscript Gwrite: Offloading Replication in Disaggregated Memory Systems
Research Manuscript SSD Reforge: Dynamic Parity Management to Extend SSD Lifetime Under Aging
Research Manuscript Chimera: A Unified FHE Accelerator with Enhanced Compatibility for TFHE
Research Manuscript Parallel Combinational Equivalence Checking Through Factored Form Sharing
Engineering Presentation AI-Enabled EDA Cloud Infrastructure and Design Optimization for Next-Generation Semiconductor Design
Research Manuscript Inferweave: Efficient LLM Inference on the MT-3000 Processor
Research Manuscript Where Biology Meets Computation: Next‑Gen Bio‑Cyber‑Physical Innovations
Research Manuscript STAC: Spatial-Temporal Activation Contextualization for Resilient LLM Inference
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript Attestllm: Efficient Attestation Framework for Billion-Scale On-Device LLMs
Research Manuscript Per Flow Asynchronous Traffic Shaping in Time Sensitive Networking
Research Manuscript EASY-ZKP: An End-to-End FPGA-Accelerated System for Zero Knowledge Proofs
Research Manuscript Legend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
Research Manuscript TDH-GNN: An Efficient Topology-Driven Accelerator for Dynamic Heterogeneous GNN
China
Research Manuscript PRS: An Efficient Parallel SAT Framework
Research Manuscript Floquet-Based Subspace Projection Method for Time-Domain PPV Computation
Research Manuscript COLA: Enabling Low-Latency Reads for Flash-Based SSDs via Code Length Adaptation
China
Research Manuscript Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Research Manuscript TierANNS: Scalable Graph-Based ANNS with CXL-Enabled Tiered Data Placement
Research Manuscript Slcross: Cross-Component System-Level Cache Side-Channel Attacks on Apple M2 SoC
Research Manuscript Towards Practical Live Migration for Heterogeneous Confidential Virtual Machines
Research Manuscript A Locality-Aware Temporal Motif Mining Accelerator with Chunk-Based Search Tree Expansion
Research Manuscript PiHG: A Redundancy-Free Heterogeneous Graph Neural Network Accelerator via a Pivot-Centric Approach
Research Manuscript TDH-GNN: An Efficient Topology-Driven Accelerator for Dynamic Heterogeneous GNN
Research Manuscript Exploiting Dependency and Parallelism: Real-Time Scheduling and Analysis for GPU Tasks
Research Manuscript Operator-Level Acceleration for Sparse 3D Object Detection
Research Manuscript Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
Research Manuscript Securerouter: Encrypted Routing for Efficient Secure Inference
Research Manuscript BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis
Late Breaking Results Late Breaking Results: "describing" Your Way to a Functional Microfluidic Chip
Work in Progress Late Breaking Results: A Scalable and Efficient Multi-Layer 3D-Printed Microfluidic Design Synthesis
Research Manuscript AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning
Research Manuscript KERV: Kinematic-Rectified Speculative Decoding for Embodied VLA Models
Research Manuscript Optimizing Dynamic-Shape Neural Networks: A Unified Approach to Adaptive Tuning
Research Manuscript GPU-Fuzz: Finding Memory Errors in Deep Learning Frameworks
China
Research Manuscript PMU-Faker: The Apparently Harmless Performance Monitoring Unit Events Are Actually Harmful
Research Manuscript Unveiling the Security Risks Driven by the Hardware Interrupts
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Research Manuscript Lhgstore: An In-Memory Learned Graph Storage for Fast Updates and Analytics
Research Manuscript PLONK-Hammer:breaking Input Privacy of PLONK Proving Systems via Rowhammer
Research Manuscript Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
Engineering Poster Accelerating IR and Timing Convergence with Revolutionary IR-ECO
Research Manuscript Integrated Timing-Driven Placement for Hybrid-Bonding-Based Face-to-Face 3D ICs
Research Manuscript TRIDENT: An End-to-End Streaming Accelerator for TriSpGEMM
Research Manuscript A Locality-Aware Temporal Motif Mining Accelerator with Chunk-Based Search Tree Expansion
Research Manuscript PiHG: A Redundancy-Free Heterogeneous Graph Neural Network Accelerator via a Pivot-Centric Approach
Research Manuscript TDH-GNN: An Efficient Topology-Driven Accelerator for Dynamic Heterogeneous GNN
Research Manuscript PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript Parallel Combinational Equivalence Checking via Sweeping-Based Task Scheduling
Research Manuscript Pipegs: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning
Research Manuscript SpRDA: An Efficient Sparse Accelerator for Robotics Diffusion Model
Research Manuscript Beyond Exact: Tight WCET Analysis of GPU Kernels with Branch Divergence
Research Manuscript Exploiting Dependency and Parallelism: Real-Time Scheduling and Analysis for GPU Tasks
Research Manuscript RM Poster Session Five
Research Manuscript Scaling the Bedrock: OS-Hardware Co-Design for High-Reliability Storage
Research Manuscript A Hamiltonian-Guided Pre-Trainer for Variational Quantum Algorithms
Research Manuscript BSGCN: Taming Diverse Sparsities in GCNs via Adaptive Band-Segmentation and Tailored Caching
Research Manuscript BiBNN: 88.6% Computation Reduction in Bayesian Neural Networks via Post-Training Bernoullization
Research Manuscript Hybrid PIM-Oriented Architecture-Dataflow Co-Design for Heterogeneous LLM Inference
Research Manuscript TRIDENT: An End-to-End Streaming Accelerator for TriSpGEMM
Engineering Poster Gladiator Cost-Based Partial Subgraph Matching for Circuit Pattern Recognition
Engineering Presentation Graph Isomorphism for Explainable Transistor-Level Circuit Comparison
Research Manuscript Strix: Re-Thinking NPU Reliability from a System Perspective
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
China
Research Manuscript PMU-Faker: The Apparently Harmless Performance Monitoring Unit Events Are Actually Harmful
Research Manuscript Unveiling the Security Risks Driven by the Hardware Interrupts
Research Manuscript Attestllm: Efficient Attestation Framework for Billion-Scale On-Device LLMs
Research Manuscript PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
Research Manuscript Integrated Timing-Driven Placement for Hybrid-Bonding-Based Face-to-Face 3D ICs
Research Manuscript Self-Driving EDA: Agents, Benchmarks, and Evolving Toolchains
Research Manuscript PRISM: Dynamic Primitive-Based Forecasting for Large-Scale GPU Cluster Workloads
Research Manuscript Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence
Research Manuscript An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference
Research Manuscript Dart: Towards Redundancy-Free RTL Simulation via DAG-Driven Execution
Research Manuscript Attestllm: Efficient Attestation Framework for Billion-Scale On-Device LLMs
Research Manuscript HW-Router: Hardware-Aware Routing for Scalable Multi-LLM Serving
Research Manuscript Securerouter: Encrypted Routing for Efficient Secure Inference
Research Manuscript RM Poster Session Eight
Research Manuscript Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures
Research Manuscript Are We There Yet? That is the Question ... for Computing near and in Memory.
Research Manuscript Coordinated Clip-Wise Gradient Scheduling for Full-Chip ILT via Policy Learning
Research Manuscript DR. OPC: Differentiable Rasterization for Advanced Optical Proximity Correction
Research Manuscript Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge
Research Manuscript CODA: A Computation-Data Decoupled Dataflow Paradigm for DNN Computing on NPUs
Research Manuscript Hero: Adaptive Orchestration of Retrieval-Augmented Generation on Heterogeneous Mobile SoC
Research Manuscript Icarus's Wings: Disabling MoE Offloading Acceleration via a Universal Hidden Prefix Attack
Research Manuscript KERV: Kinematic-Rectified Speculative Decoding for Embodied VLA Models
Research Manuscript Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits
Research Manuscript TRACE: Learning to Compute on Circuit Graphs
Research Manuscript Operator-Level Acceleration for Sparse 3D Object Detection
Engineering Special Session The Heterogeneous Future of Agentic AGI: Challenges and Opportunities!
Research Manuscript Targeted Bit-Flip Attacks on LLM-Based Agents
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Engineering Poster Accelerating IR and Timing Convergence with Revolutionary IR-ECO
Engineering Presentation An Adjustable Length Compression Method for MBIST Repair Information
Research Manuscript From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
Research Manuscript Strix: Re-Thinking NPU Reliability from a System Perspective
Research Manuscript ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
Research Manuscript Circuitdiff: Bridging Netlist Knowledge with RTL Based on Graph Denoising Diffusion
Research Manuscript Insights from Verification: Training a Verilog Generation LLM Using Reinforcement Learning with Testbench Feedback
Research Manuscript Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits
Research Manuscript TRACE: Learning to Compute on Circuit Graphs
Research Manuscript Dart: Towards Redundancy-Free RTL Simulation via DAG-Driven Execution
Research Manuscript Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
Research Manuscript Ctxmem: OS-Hardware Co-Designed Tiered Memory with DRAM-SSD Hybrid CXL Devices
Research Manuscript TRIDENT: An End-to-End Streaming Accelerator for TriSpGEMM
China
Engineering Presentation Multi-Cycle Interconnect Synthesis in Small to Large Cutting Methodology
Research Manuscript GenDSE: Generative CPU Design Space Exploration via Sequential Decision Making
Research Manuscript Knowledge-Driven Hybrid SSD Management Enhanced by Fine-Tuned LLMs
Research Manuscript Edgesc: Universal Stochastic Computing Architecture for Efficient Edge Detection
Research Manuscript Optimizing Dynamic-Shape Neural Networks: A Unified Approach to Adaptive Tuning
Research Manuscript Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge
Research Manuscript Crystal-KV: Efficient KV Cache Management for Chain-of-Thought LLMs via Answer-First Principle
Research Manuscript Efficient HLS Accelerator Floorplan on Multi-Die FPGA Aided by Graph Neural Networks
Research Manuscript Idealsim: Efficient Ideal Scenario Modeling for Processor Upper-Bound Performance Analysis
Late Breaking Results Late Breaking Results: Astfusion -- Two-Stage Structural Enhancement Learning for Robust HLS Code Generation
Late Breaking Results Late Breaking Results: Efficient MoE-ViT Gating on Edge Accelerator via Dynamic Expert Routing and Quantized Router
Work in Progress Late Breaking Results: Micro-Dense Tensor-Core-Aligned N:M Sparse Kernel for Efficient Inference Acceleration
Late Breaking Results Late Breaking Results: Recoverability-Guided Layer-Wise N:M Sparsity Under Latency Constraints
Research Manuscript PFGEMM: Fully Exploiting the Parallelism of SpGEMM With Element-Wise Out-of-Order Execution Flow and Prefix Decomposition of Indices
Research Manuscript SpArC: Sparse Tensor Accelerator Compilation with Scheduling and Mapping
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript Orchestrating LLM Systems at Scale: Heterogeneity, Memory, and Throughput
Research Manuscript OpenSUN: An Open Platform for Exploring Scale-Up Network Systems
Research Manuscript How Can Reinforcement Learning Achieve Expert-Level Placement?
Research Manuscript Parallelizing Complementary Approximate Reachability
Research Manuscript Gwrite: Offloading Replication in Disaggregated Memory Systems
Research Manuscript Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits
Research Manuscript Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
Research Manuscript TRACE: Learning to Compute on Circuit Graphs
Research Manuscript Cachence: Fine-Grained Cache Partitioning in Both Time and Space
Research Manuscript Analytically-Derived Hybrid Net–pin Weighting for Timing-Driven Global Placement
Research Manuscript FLASH3D: A Fast Layered Analytical Solver for High-Accuracy Steady-State Thermal Simulation of 3D ICs
Late Breaking Results Late Breaking Results: HUSH: Silencing Inter-Core Interference in Real-Time Cache Analysis
Research Manuscript Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
Research Manuscript KL-MoE: A Hierarchical MoE Pruning Framework Exploiting KL Divergence
Research Manuscript Throughput-Oriented Speculative Decoding via Intra-Device Parallelism
Research Manuscript Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells
Research Manuscript Cell-Structure-Independent Transistor-Level Placement and MOL-Aware Routing Framework Beyond the Standard-Cell Paradigm
Late Breaking Results Late Breaking Results: A Coarse-to-Fine PCB Placement Framework via LLM-Guided Component Grouping and Group-Aware Placement
Late Breaking Results Late Breaking Results: A Fully Differentiable Rectilinear Minimum Spanning Tree Wirelength Model for Global Placement
Late Breaking Results Late Breaking Results: LLM-Driven Constraint Generation and Deferred Shape Exploration for Analog IC Floorplanning
Late Breaking Results Late Breaking Results: Merge-Aware Placement and DP-Based Wave Propagation Routing for Scalable Flip-FET Cell Layout Synthesis
Late Breaking Results Late Breaking Results: Physics-Aware Diffusion Framework for Transistor-Level Placement Beyond Standard-Cell Boundary
Late Breaking Results Late Breaking Results: Scalable OARSMT Generation via Predictive Topological Reduction in VLSI Routing
Research Manuscript Paretopilot: Global Optimization Reasoning on HLS Design Space Exploration with LLMs
Research Manuscript eLLM: Elastic Memory Management Framework for Efficient LLM Serving
Research Manuscript BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis
Research Manuscript BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs
Research Manuscript Flexicts: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs
Research Manuscript Mixed-Structure Double-Sided Redistribution Layer Routing for Glass Interposer-Based 5.5D ICs
Research Manuscript Compilation Tells Energy: Rethinking Power Modeling for DNN Accelerator Agile Design
Research Manuscript FreqSEM: Frequency-Aware High-Precision Contour Extraction for Lithographic SEM Images
Research Manuscript From Fab to Mask Shop: A Differentiable MDP-ILT Framework for Co-Optimization of Wafer Pattern Fidelity and Mask Writability
Research Manuscript Stitch: Assertion-Guided Patching of On-Chip Protocol Implementations Using LLMs
Research Special Session Stacked, Packed, and Fully Tested: Advanced Packaging Done Right
Engineering Poster Accelerating IR and Timing Convergence with Revolutionary IR-ECO